Asynchronous transfer mode adapter for desktop applications

• US 5,548,587 A
• Filed: 09/12/1994
• Issued: 08/20/1996
• Est. Priority Date: 09/12/1994
• Status: Expired due to Term

• Current Assignee: Sagemcom Broadband SAS (Sagemcom Holding SAS)
• Original Assignee: Efficient Networks, Inc. (Siemens AG)
• Inventors: Dibble, Kevin S., Fosmark, Klaus S., Bailey, Chase B., Perry, William A., Lauffenberger, Kenneth A.
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): NGO, RICKY QUOC
• Application Number:
  US08/304,349
• Time in Patent Office: 708 Days
• Field of Search: 370/60, 370/13, 370/79, 370/17, 370/91, 370/85.1, 370/85.13, 370/60.1, 370/61, 370/58.1, 370/58.2, 370/67, 370/85.14, 370/94.1, 370/94.2, 370/110.1, 395/200, 395/325, 395/425, 395/500, 395/725, 395/800
• US Class Current: 370/395.7
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/563 Signalling, e.g. protocols, reference model
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5658 using the AAL5
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An ATM adapter for desktop applications includes an adapter for interfacing an ATM network. The adapter includes an ATM application specific integrated circuit (ASIC). The ATM ASIC may interface with a data bus such as an SBus using a host interface circuit. The host interface circuit includes a bus interface, a DMA controller and a slave access controller. The DMA controller controls DMA operations within the ATM ASIC and associates with a RAM interface arbiter. The slave access controller controls operation of an interrupt circuit that goes to the SBus as well as a statistics circuit. The RAM interface arbiter arbitrates communication between the DMA controller, the slave access control circuit, a segmentation engine, and a reassembly engine. The RAM interface arbiter communicates with the RAM bus to a RAM associated with an adapter. The segmentation engine segments data into ATM format for transfer through a physical interface circuit. The physical interface circuit also receives formatted ATM information and sends that information to the reassembly engine. The reassembly engine reassembles the ATM data and transmits it through the RAM interface/arbiter circuit to the RAM bus. From the RAM bus, data may pass again through the RAM interface/arbiter to the DMA controller and onto the SBus through the host bus interface.

Claims

1. An ATM adapter for adapting a desktop user station to a local ATM network, comprising:

an adapter for interfacing said local ATM network, said adapter comprising an ATM integrated circuit for interfacing between a host device data bus and a local ATM network physical layer, said ATM integrated circuit, comprising;

a host interface circuit comprising a bus interface circuit, a DMA control circuit and a slave access control circuit, said bus interface circuit for interfacing said data host device bus, said DMA control circuit for controlling memory access operations between said ATM integrated circuit and associating with a RAM interface/arbiter interface circuit, said slave access control circuit for controlling operation of an interrupt circuit and a statistics circuit;

a segmentation engine associated with said RAM/interface arbiter circuit for segmenting data from said host device data bus into ATM cells in preparation for said data to be transferred transfer on said local ATM network;

a reassembly engine associated with said RAM/interface arbiter circuit for reassembling ATM cells from said local ATM network into data suitable for transfer to said host device data bus;

said RAM interface/arbiter circuit for interfacing said DMA control circuit, said slave access control circuit, said segmentation engine, and said reassembly engine with a memory circuit associated with said ATM integrated circuit; and

a physical interface circuit associated between said segmentation engine and said reassembly engine on a first interface and the local ATM network on a second interface for interfacing said ATM integrated circuit physically with said local ATM network;

further wherein said host interface circuit, said physical interface circuit, said segmentation engine, said reassembly engine, and said RAM interface/arbiter circuit are formed as an integrated circuit.

2. The asynchronous transfer mode adapter circuit of claim 1, further comprising a memory arbiter circuit for arbitrating access to said memory from among said memory access controller, said slave access control circuit, said segmentation engine, and said reassembly engine.

3. The asynchronous transfer mode adapter circuit of claim 1, wherein said integrated circuit transmits ATM cells as protocol data units.

4. The asynchronous transfer mode adapter circuit of claim 1, wherein said adapter supports both AAL5 and non-AAL5 transfer modes.

5. The asynchronous transfer mode adapter circuit of claim 1, wherein said segmentation engine uses predefined descriptors for avoiding the transfer of meaningless information, while moving pointers for indicating the receipt and processing of ATM cells.

6. The asynchronous transfer mode adapter circuit of claim 1, further comprising circuitry for supporting AAL5 conformance protocols at a common part convergence sublayer.

7. The asynchronous transfer mode adapter circuit of claim 1, further comprising AAL5 conformance protocols in said segmentation engine.

8. The asynchronous transfer mode adapter circuit of claim 1, further comprising AAL5 conformance protocols in said reassembly engine.

9. The asynchronous transfer mode adapter circuit of claim 1, wherein said physical interface circuit comprises circuitry for interfacing a Utopia interface.

10. The asynchronous transfer mode adapter circuit of claim 1, further comprising circuitry for communicating operation and maintenance cells with said local area network.

11. The asynchronous transfer mode adapter circuit of claim 1, further comprising peak cell rate circuitry within said segmentation engine for shaping traffic flow within said segmentation engine.

12. The asynchronous transfer mode adapter circuit of claim 1, wherein said segmentation engine segments eight channels of data simultaneously for transfer on said local area network.

13. The asynchronous transfer mode adapter circuit of claim 1, wherein said reassembly engine comprises circuitry for reassembling 1024 cells within said integrated circuit.

14. The asynchronous transfer mode adapter circuit of claim 1, wherein said reassembly engine provides ten bits of virtual channel identifier space.

15. An ATM adapter for desktop applications having an ATM integrated circuit, said ATM integrated circuit comprising:

a host interface circuit for interfacing a host device, said host interface circuit comprising a host device bus interface circuit, a DMA control circuit, and a slave access control circuit;

said host device bus interface circuit for interfacing said host interface circuit with a host device data bus for communicating host device data between said host interface circuit and said host device data bus;

said DMA control circuit associated with said bus interface circuit for controlling DMA operations associated with said host device data;

said slave access control circuit associated with said bus interface circuit for controlling operations of said host interface circuit relating to host device bus interrupts and statistics;

a physical interface circuit associated with an ATM physical layer for communicating ATM formatted data with a local ATM network;

a segmentation engine associated with said physical interface circuit for transmitting ATM formatted data to said physical interface circuit, said segmentation engine associated further for receiving said host device data and segmenting said host device data to form outgoing ATM formatted data;

a reassembly engine associated with said physical interface circuit for receiving incoming ATM formatted data from said local ATM network and generating therefrom from host device data for transmission to said host interface circuit;

a RAM interface/arbiter circuit associated with a RAM bus for communicating with a RAM, said RAM interface/arbiter circuit further associated with said DMA control circuit, said slave access control circuit, said segmentation engine and said reassembly engine for interfacing and arbitrating access to said RAM of signals communicated with said DMA control circuit, said slave access control circuit, said segmentation engine, and said reassembly engine; and

further wherein said host interface circuit, said physical interface circuit, said segmentation engine, said reassembly engine, and said RAM interface/arbiter circuit are formed as an integrated circuit.

16. The ATM integrated circuit of claim 15, wherein said segmentation engine segments AAL5 traffic and further wherein said physical interface circuit communicates AAL5 traffic with the local ATM network.

17. The ATM integrated circuit of claim 15, wherein said segmentation engine segments traffic other than AAL5 traffic and further wherein said physical interface circuit transmits to the local ATM network traffic other than AAL5 traffic.

18. The ATM integrated circuit of claim 15, wherein said segmentation engine further comprises a segmentation buffer, said segmentation buffer further comprising a segmentation buffer descriptor portion and a data portion for receiving data to be segmented into ATM formatted data.

19. The ATM integrated circuit of claim 15, wherein said segmentation engine further performs traffic shaping in response to a pre-scale parameter and a rate resolution parameter.

20. The ATM integrated circuit of claim 15, wherein said reassembly engine updates a service list describing completed reassembly operations on said ATM formatted data.

21. The ATM integrated circuit of claim 15, wherein said segmentation engine further comprises circuitry for performing the steps of:

enqueueing a protocol data unit for the DMA control circuit;

reading a queue in response to the enqueued protocol data unit;

segmenting the protocol data unit; and

providing data to said host interface circuit in response to said segmented protocol data unit.

22. The ATM integrated circuit of claim 15, wherein said reassembly engine further comprises circuitry for performing the steps of:

receiving a host device data from said host interface circuit;

enqueueing a DMA receive queue in response to said host device data;

reading a DMA receive queue from a memory map associated with said DMA control circuit;

receiving an operation and maintenance cell through said physical interface circuit;

responding to a change signal from said host interface circuit; and

receiving an incomplete cell from said host interface circuit.

23. The ATM integrated circuit of claim 15, further comprising circuitry for supporting operation and maintenance cells associated with said local ATM network.

24. The ATM integrated circuit of claim 15, further comprising circuitry for permitting simultaneous operation of at least eight segmentation channels from said RAM interface/arbiter circuit and at least 1,024 reassembly operations on said ATM formatted data.

25. The ATM integrated circuit of claim 15, further comprising circuitry for processing virtual channel identifier and virtual path identifier information.

26. The ATM integrated circuit of claim 15, further comprising circuitry for shaping peak cell rate traffic.

27. The ATM integrated circuit of claim 15, further comprising circuitry for inserting ATM cell header fields in association with said ATM formatted data that is to be communicated on said local ATM network.

28. The ATM integrated circuit of claim 15, further comprising circuit for allocating reassembly buffer space associated with said reassembly engine and wherein said host interface circuitry further comprises circuitry for notifying the host device data bus of the receipt of information from said local ATM network.

29. The ATM integrated circuit of claim 15, further comprising circuitry for reporting status of said ATM integrated circuit and for reporting errors associated with operation of said ATM integrated circuit.

30. The ATM integrated circuit of claim 15, further comprising interface circuitry for associating said physical interface circuitry with a UTOPIA interface.

31. The ATM integrated circuit of claim 15, wherein said physical interface circuit further comprises circuitry for operating in a non-pipelined read UTOPIA mode.

32. The ATM integrated circuit of claim 15, wherein said physical interface circuit further comprises circuitry for operating in an asynchronous interface mode.

33. The ATM integrated circuit of claim 15, wherein said physical interface circuit further comprises a mode control register for controlling the operational mode of said physical interface circuit.

34. The ATM integrated circuit of claim 15, wherein said slave access control circuit further comprises circuitry for accessing adapter memory associated with said memory circuit and memory associated with internal registers within said ATM integrated circuit in response to addresses determined by said host interface circuit.

35. The ATM integrated circuit of claim 15, wherein said integrated circuit comprises circuitry for responding to local ATM network data having the types of byte burst, half-word burst, word burst, two-word burst, four-word burst, eight-word burst, and sixteen-word burst.

36. The integrated circuit of claim 15, wherein said host interface circuit associates for generating a words-maybe cycle including a complete burst, a portion of said complete burst having data that will be ignored by said host device.

37. The ATM integrated circuit of claim 15, wherein said host interface circuit further comprises a statistics circuit for maintaining a plurality of statistics counters of trashed cells.

38. The ATM integrated circuit of claim 15, wherein said host interface circuit further comprises a statistics circuit, said statistics circuit comprising a virtual channel identifier trash counter circuit comprising an overflow trash counter.

39. The ATM integrated circuit of claim 15, wherein said host interface circuit further comprises interrupt circuitry for processing interrupt generation.

40. The ATM circuit of claim 15, wherein said host interface circuit further comprises interrupt circuitry, said interrupt circuitry further comprising circuitry for responding to interrupts arising from an event within said ATM integrated circuit and further comprising circuitry responsive to interrupts arising from an external source associated with said physical interface circuit.

41. The ATM integrated circuit of claim 15, wherein said DMA control circuit further comprises circuitry for shaping traffic in response to a peak cell rate counter circuit for traffic on a single segmentation channel associated with said segmentation engine.

42. The ATM integrated circuit of claim 15, wherein said DMA control circuit further comprises an arbiter-multiplexor circuit associated with said DMA control circuit for shaping traffic across a plurality of segmentation channels associated with said segmentation engine.