On-board diagnostic testing

• US 5,548,713 A
• Filed: 07/08/1994
• Issued: 08/20/1996
• Est. Priority Date: 10/15/1991
• Status: Expired due to Fees

• Current Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Keeley, James W., Hirsch, Thomas S., Petry, Keith L.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): KEMPER, MELANIE A
• Application Number:
  US08/272,893
• Time in Patent Office: 774 Days
• Field of Search: 371/22.5, 371/22.6, 371/16.1, 371/18, 371/25.1, 371/15.1, 371/16.5, 364/483, 395/575, 324/731
• US Class Current: 714/25
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2273 Test methods

Abstract

A processing unit couples to a system bus and includes a microprocessor which tightly couples to a local memory. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which couples to the microprocessor and to the system bus. The EEPROM unit stores in first and second separate regions, on-board diagnostic (OBD) routines and boot routines, respectively. The OBD routines are organized into a plurality of categories or phases. The processing unit includes a register accessible only by the microprocessor which, under the control of the OBD routines, is loaded with a number of predetermined values at the beginning of each individual OBD routine for identifying a particular phase and subphase of testing to be performed. Means coupled to the register is directly connected to display a first phase portion of the contents of the register for indicating during which phase of testing a failure occurred. The phase and subphase contents of the register are used to identify the actual test which failed. This information provides an index into a test dictionary which indicates the specific component or group of components which failed.

Claims

1. A method of organizing and testing a processing unit board within either a system or a factory test environment, said board when installed in said system environment, being coupled to a system bus of the system in common with a number of other processing units, said board including a plurality of major parts, one of which is a high speed microprocessor, said microprocessor having an internal cache memory, memory management unit and a control read only memory for issuing commands locally and externally to said system bus, an internal register accessible only by said microprocessor and a local memory coupled to said microprocessor and to said system bus, said method comprising the steps of:

(a) including in said processing unit board, an electrically erasable programmable read only (EEPROM) unit which is connected to said microprocessor and to said system bus when installed in said system;

(b) storing in said EEPROM unit, a plurality of on-board diagnostic (OBD) routines organized in a predetermined manner for extensively testing the operability of said processing unit board, each OBD routine containing a number of tests containing a number of software instructions;

(c) accessing each of said plurality of OBD routines in a predetermined ordered sequence by said microprocessor at high speed for carrying out a different phase and subphases of testing on a predetermined part of one of said major parts of said processing unit board upon being powered on by said system or in response to a command from said system bus specifying running of said OBD routines;

(d) generating a different predetermined code at a beginning of each OBD routine for designating the phase and subphase of testing being executed by said processing unit board, said different predetermined code having a numerical value which indicates the amount of testing which has been completed;

(e) storing said each different predetermined code generated in step (d) in said internal register during execution of a corresponding one of said OBD routines; and

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(f) connecting said internal register to an indicator panel for visually displaying said different predetermined code for both indicating which phase of testing could not be successfully executed by said microprocessor and the extent to which said testing has been completed enabling an operator to make a visual determination as to whether said processing unit board or major part is to be replaced.

(g) executing a local memory test routine by said microprocessor for verifying the operability of a small area within said local memory; and

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(h) copying said OBD routines into said small area of local memory verified as good in step (g) for enabling execution of subsequent OBD routines to proceed at maximum speed.

2. The method of claim 1 wherein said different predetermined code includes first and second portions, said first portion corresponding to a phase code for identifying said phase of testing visually indicating the extent to which testing has been completed and said second portion corresponding to a subphase code for identifying a specific test and subphase of testing being executed by said microprocessor.

3. The method of claim 1 wherein said predetermined manner corresponds to organizing said plurality of OBD routines into a corresponding number of sequential files for executing by said microprocessor in sequential order which defines said different phases of testing starting from a highest phase to a zero phase.

4. The method of claim 1 wherein prior to executing step (c), said microprocessor performs an internal self test procedure for verifying the operation of said components and performs step (c) only upon successful completion of said procedure.

5. A method of organizing and testing a processing unit board within either a system or a factory test environment, said board when installed in said system environment, being coupled to a system bus of the system in common with a number of other processing units, said board including a plurality of major parts, one of which is a high speed microprocessor, said microprocessor having an internal cache memory, memory management unit and a control read only memory for issuing commands locally and externally to said system bus, said method comprising the steps of:

(a) including in said processing unit board, an electrically erasable programmable read only (EEPROM) unit which is connected to said microprocessor and to said system bus when installed in said system;

(b) storing in said EEPROM unit, a plurality of on-board diagnostic (OBD) routines organized in a predetermined manner for extensively testing the operability of said processing unit board, each OBD routine containing a number of tests containing a number of software instructions;

(c) accessing each of said plurality of OBD routines in a predetermined ordered sequence by said microprocessor at high speed for carrying out a different phase and subphases of testing on a predetermined part of one of said major parts of said processing unit board upon being powered on by said system or in response to a command from said system bus specifying running of said OBD routines;

(d) generating a different predetermined code at a beginning of each OBD routine for designating the phase and subphase of testing being executed by said processing unit board, said different predetermined code having a numerical value which indicates the amount of testing which has been completed;

(e) displaying said different predetermined code during executing of said OBD routines by said microprocessor for enabling an operator to make a visual determination as to whether said processing unit board or major part is to be replaced in addition to the extent of testing which has been completed;

(f) executing said number of tests of each of said plurality of OBD test routines during a corresponding number of subphases;

(g) including as part of said plurality of OBD routines, a subphase generation routine for generating said different predetermined code designating which subphase of testing is being carried out, said subphase generation routine when executed by said microprocessor generates said proper different predetermined code by combining a generated phase code value with a subphase parameter value received from a last executed one of said number of said tests and shifting a combined result by a predetermined number of bit positions for proper alignment during display;

(h) including in each OBD routine, a number of subroutine calls to said subphase generation routine, said number of subroutine calls corresponding in number to said number of tests contained in said each OBD routine for generating the proper different predetermined code prior to execution of each of said number of tests for designating said subphases; and

wherein said system further includes analysis equipment operatively coupled to said processing unit board for determining which part of said processing unit board is faulty and said method further including the steps of;

(i) storing in said analysis equipment, a test dictionary containing a plurality of descriptions of the faulty components detectable by each of said plurality of OBD routines; and

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(j) accessing said test dictionary by said analysis equipment upon detecting an error condition using said different predetermined code when testing was stopped by said microprocessor for determining which major part components should be replaced.

6. The method of claim 5 wherein said analysis equipment is a personal computer or analyzer apparatus.

7. A method of organizing and testing a processing unit board within either a system or a factory test environment, said board when installed in said system environment, being coupled to a system bus of a system in common with a number of other processing units, said board including a plurality of major parts, one of which is a high speed microprocessor, said microprocessor having an internal cache memory, memory management unit and control read only memory for issuing commands locally and externally to said system bus, said method comprising the steps of:

(a) including in said processing unit board, an electrically erasable programmable read only (EEPROM) unit which is connected to said microprocessor and to said system bus when installed in said system;

(b) storing in said EEPROM unit, a plurality of on-board diagnostic (OBD) routines organized in a predetermined manner for extensively testing the operability of said processing unit board, each OBD routine containing a number of tests containing a number of software instructions;

(c) accessing each of said plurality of OBD routines in a predetermined ordered sequence by said microprocessor at high speed for carrying out a different phase and subphases of testing on a predetermined part of one of said major parts of said processing unit board upon being powered on by said system or in response to a command from said system bus specifying running of said OBD routines;

(d) generating a different predetermined code at a beginning of each OBD routine for designating the phase and subphase of testing being executed by said processing unit board, said different predetermined code having a numerical value which indicates the amount of testing which has been completed; and

,

(e) displaying said different predetermined code during executing of said OBD routines by said microprocessor for enabling an operator to make a visual determination as to whether said processing unit board or major part is to be replaced in addition to the extent of testing which has been completed;

(f) including in said plurality of OBD routines, a number of external tests specifying the generation of different I/O commands to said system bus designating said processing unit; and

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(g) executing said number of external tests by said microprocessor for verifying that said processing unit is able to communicate with other units connected to said system bus.

8. A system for testing a processing unit board of a system within either a system or factory environment, said processing unit board including a plurality of major parts one of which is a microprocessor coupled to a local bus, said microprocessor including a plurality of components which include an internal cache memory, memory management unit and control read only memory for issuing commands locally, said local bus being coupled to said system bus in common with a number of other processing units for issuing commands externally to said system bus, said board further comprising:

an electrically erasable programmable read only memory (EEPROM) unit coupled to said system bus, said EEPROM unit including a plurality of locations for storing software instructions of a plurality of on-board diagnostic (OBD) routines, each containing a number of subtests organized to be executed in a predetermined order corresponding to a number of testing phases and subphases for extensively testing said plurality of major parts of said board further comprising;

means coupling said EEPROM unit to said microprocessor;

internal register means coupled to said microprocessor for storing a different predetermined code designating said phases generated by said microprocessor at a beginning of each OBD routine and subphases generated during execution of said each OBD routine for designating which testing phase and subphase within said phase is being executed, said different predetermined code having a numerical value which indicates the amount of testing which has been completed, said internal register means including first and second sections, said first section being coupled to said microprocessor and in response to each I/O command from said microprocessor designating a write operation to said internal register means, storing one of said predetermined .codes until receipt of a next I/O command designating a write operation to said register and said second section being coupled to said first section and to said microprocessor, said second section in response to each I/O command designating a read operation to said internal register means, transferring predetermined information contained in said first section stored in conjunction with performing another function to said microprocessor for carrying out said another function; and

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display means coupled to said internal register means for displaying said different predetermined code for enabling an operator to make a visual determination as to whether said processing unit board or which major part should be replaced and said extent of testing which has been completed.

9. The system of claim 8 wherein said OBD routines being executed by said microprocessor follows successful execution of an internal self test procedure by said microprocessor which verifies the operability of said plurality of components.

10. The system of claim 8 wherein said processing unit board includes a clock generator for generating a reference clock signal for synchronizing operations within said processing unit board and wherein said first section includes a programmable array logic (PAL) circuit coupled to said clock generator for receiving said reference clock signal and said PAL circuit including register circuits for storing each of said predetermined codes in response to said reference clock signal.

11. The system of claim 10 wherein said PAL circuit couples to said display means, said PAL circuit in response to said reference clock signal applying signals to said display means indicating the phase of testing being performed by said microprocessor.

12. The system of claim 10 wherein said other function is to store channel information used in issuing I/O commands to said system bus.