Dynamic load balancing for a multiprocessor pipeline by sorting instructions based on predetermined execution time

• US 5,548,737 A
• Filed: 04/11/1995
• Issued: 08/20/1996
• Est. Priority Date: 07/10/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Edrington, Jimmie D., Einkauf, Mark A., Jensen, Allen P., Vanover, Michael T.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US08/421,632
• Time in Patent Office: 497 Days
• Field of Search: 395/375, 395/650, 395/775, 395/163
• US Class Current: 712/200
• CPC Class Codes: G06F 2209/5017 Task decomposition
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5055 considering software capabilities, i.e. software resources associated or available to the machine
• CPC Class Codes: Y02P 20/129 Energy recovery, e.g. by cogeneration, H2recovery or pressure recovery turbines

Abstract

An apparatus for processing high level instructions including a plurality of processing units, means for generating a plurality of instructions to perform said high level instructions, and means for dynamically organizing said generated instructions into at least one group, each group including at least one instruction to be processed by one of said processing units. In addition, a method of processing high level instructions by a plurality of processing units including generating a plurality of instructions to perform said high level instructions, and dynamically organizing said generated instructions into at least one group, each group including at least one instruction to be processed by one of said processing units.

Claims

1. An apparatus for processing high level instructions comprising:

a) a plurality of processing units including at least a first processsing unit and a second processing unit;

b) means for generating a plurality of instructions to perform a high level instruction;

c) means for predetermining a length of time for processing each said generated instruction; and

means, coupled to the predetermining means, for dynamically organizing said generated instructions into at least a first group and a second group based on the predetermined length of time for processing each instruction, each instruction in said first group to be processed by said first processing unit prior to any instructions of said second group being processed by said second processing unit, each group including at least one instruction to be processed by one of said plurality of processing units.

2. The apparatus of claim 1 wherein said processing units include means for processing each instruction in each said group of instructions sequentially.

3. The apparatus of claim 2 further comprising means for coupling said processing units into at least one serial chain.

4. The apparatus of claim 3 further comprising means for coupling said processing units into a plurality of serial chains.

5. The apparatus of claim 3 further comprising means, coupled to the organizing means, for providing an organization description of said processing units.

6. The apparatus of claim 5 wherein the organizing means includes means for dynamically organizing the instructions into said groups based on the predetermined length of time for processing each instruction and the provided organizing description of said processing units.

7. the apparatus of claim 6 wherein at least one of said processing units includes a plurality of processors.

8. The apparatus of claim 6 further comprising means, coupled to the organizing means, for providing a description of memory resources available for each of said processing units.

9. The apparatus of claim 1 further comprising means for distributing each said group of instructions to one of said processing units for processing.

10. The apparatus of claim 1 wherein said means for predetermined includes predetermining an order of execution for processing each instruction and wherein said means for dynamically organizing includes dynamically organizing said generated instructions into at least one group based on the predetermined order of execution.

11. A computer implemented method of processing high level instructions by plurality of processing units, comprising the steps of:

a) generating a plurality of instructions to perform a high level instruction;

b) predetermining a length of time for processing each said generated instruction; and

c) dynamically organizing said generated instructions into at least a first group and a second group memory based on the predetermined length of time for processing each instruction, each instruction in said first group to be processed by said first processing unit prior to any instructions of said second group being processed by said second processing unit, each group including at least one instruction for processing by one of said plurality of processing units.

12. The method of claim 11 further comprising the step of processing each instruction in each said group of instructions sequentially.

13. The method of claim 12 further comprising the step of processing said groups sequentially by said processing units.

14. The method of claim 13 further comprising the step of providing an organization description of said processing units.

15. The method of claim 14 wherein the step of organizing includes dynamically organizing the instructions into said groups based on the predetermined length of time for processing each instruction and the provided organization description of said processing units.

16. The method of claim 15 further comprising the step of providing a description of memory resources available for each of said processing units.

17. The method of claim 11 further comprising a step of distributing each said group of instructions to one of said processing units for processing.

18. The method of claim 11 wherein said steps of predetermining includes predetermining an order of execution for processing each instruction and wherein said steps of dynamically organizing includes dynamically organizing said generated instructions into at least one group based on the predetermined order of execution.

19. An apparatus for processing high level instructions comprising a computer system including:

a) a plurality of processing units;

b) means for generating a plurality of instructions to perform a high level instruction;

c) means for predetermining a length of time for processing each said generated instruction; and

d) means, coupled to said predetermining means, for dynamically organizing said generated instructions into at least a first group and a second group based on the predetermined length of time for processing each instruction, each instruction in said first group to be processed by said first processing unit prior to any instructions of said second group being processed by said second processing unit, each group including at least one instruction to be processed by one of said plurality of processing units.

20. The apparatus of claim 19 wherein said processing units include means for processing each instruction in each said group of instructions sequentially.

21. The apparatus of claim 20 wherein the computer system further includes means for coupling said processors into at least one of serial chain.

22. The apparatus of claim 21 wherein the computer system further includes means for coupling said processing units into a plurality of serial chains.

23. The apparatus of claim 21 wherein the computer system further includes means, coupled to the organizing means, for providing an organization description of said processing units.

24. The apparatus of claim 23 wherein the organizing means includes means for dynamically organizing said instructions into said groups based on the predetermined length of time for processing each instruction and the provided description of said processing units.

25. The apparatus of claim 24 wherein at least one of said processing units includes plurality of processors.

26. The apparatus of claim 24 wherein the computer system further includes means, coupled to the grouping means, for providing a description of memory resources available for each of said processing units.

27. The apparatus of claim 19 further comprising means for distributing each said group of instructions to one of said processing units for processing.

28. The apparatus of claim 19 wherein said means for predetermining includes predetermining an order of execution for processing each instruction and wherein said means for dynamically organizing includes dynamically organizing said generated instructions into at least one group based on the predetermined order of execution.