Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using address page crossing predictive annotations

• US 5,548,739 A
• Filed: 11/04/1993
• Issued: 08/20/1996
• Est. Priority Date: 11/04/1993
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Yung, Robert
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/148,685
• Time in Patent Office: 1,020 Days
• Field of Search: 395/414, 395/481, 395/464, 395/465, 395/466, 395/474, 395/479
• US Class Current: 711/204
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 2212/655 Same page detection

Abstract

In a computer system having a number of page partitioned and virtually addressed address spaces, a physically addressed data storage structure and its complementary selection data storage structure is provided with a complementary memory page crossing prediction storage structure, a latch, and a comparator. The memory page crossing prediction storage structure is used to store a number of memory page crossing predictive annotations corresponding to the contents of the data and selection data storage structures. Each memory page crossing predictive annotation predicts whether the current access crosses into a new memory page. The latch is used to successively record a first portion of each accessing physical address translated from a corresponding portion of each accessing virtual address. The recorded first portion of the physical address of the immediately preceding access is used to select data currently being read out of the storage structures, if the memory page crossing predictive annotation currently being read out predicts no memory page crossing. The comparator is used to determine whether the first portions of the physical addresses of the current and immediately preceding accesses are equal, if the first portion of the physical address of the immediately preceding access is used to select data for the current access. Remedial actions including invalidating the selected data and correcting the incorrect memory page crossing predictive annotation are taken, if the two physical address portions are determined to be unequal. As a result, most of the data retrievals are made without having to wait for the first portions of the accessing physical addresses to be translated, thereby improving the performance of retrieving data from the physically addressed data storage structure.

Claims

1. In a computer system comprising a data storage structure having a plurality of data vectors, said data storage structure being physically addressed with physical addresses of a physical address space partitioned into a plurality of address pages, and each of said plurality of data vectors having a plurality of data blocks, wherein a currently addressed one of said plurality of data vectors is retrieved during a current access based on a first portion of a current physical address of the current access, a method for rapidly retrieving data from said data storage structure, said method comprising the steps of:

a) storing a plurality of description vectors corresponding to said plurality of data vectors in a description storage structure, the description storage structure being physically addressed with said physical addresses also, each of said plurality of description vectors comprising a plurality of descriptors corresponding to said plurality of data blocks;

b) storing a plurality of predictive annotations corresponding to said plurality of data vectors in a predictive annotation storage structure, the predictive annotation storage structure being physically addressed with said physical addresses also, each of said plurality of predictive annotations predicting whether a next access will cross into a new address page;

c) retrieving a corresponding one of said plurality of descriptors and a corresponding one of said plurality of predictive annotations concurrently with the current retrieval of the currently addressed data vector based on the first portion of the current physical address during the current access; and

d) selecting a data block from the currently retrieved data vector based on either a second portion of the current physical address of the current access or a second portion of a prior physical address of a prior access, depending on whether a retrieved predictive annotation predicts address page crossing or not, the retrieved predictive annotation being retrieved during either the current or an earlier access, and whether the retrieved predictive annotation of the current access or the retrieved predictive annotation of an earlier access, including which particular earlier access, is to be used for the data block selection is predetermined.

2. The method as set forth in claim 1, wherein, said method further comprises the steps of:

e) conditionally determining whether the second portions of the physical addresses of the current and the recorded preceding accesses are identical, in accordance to the predictive annotation retrieved for the immediately preceding access; and

f) conditionally correcting the predictive annotation retrieved for the immediately preceding access in said predictive annotation storage structure, in accordance to the conditional determination results.

3. The method as set forth in claim 2, wherein,

said selection data storage and said predictive annotation structures are logical subsets of a merged selection data and predictive annotation storage structure;

and

each of said selection data vector and its corresponding predictive annotation are logical subsets of a merged selection data and predictive annotation vector.

4. The method as set forth in claim 2, wherein,

said computer system has a memory space partitioned into memory pages;

said physically addressed data storage structure is a cache array of a physically addressed n-way set associative instruction cache, said data vectors being cache lines, n being an integer greater than or equal to one;

said physically addressed selection storage structure in said step a) is a cache tag array of said physically addressed n-way set associative instruction cache, said selection data vectors being cache tag entries, said selection data being address tags with associated control information; and

the first and second portions of the physical addresses are lower and higher ordered bits of the physical addresses respectively.

5. The method as set forth in claim 4, wherein,

said instruction block selection in said step c) is performed using the second portion of the recorded preceding physical address of the recorded preceding access if the predictive annotation retrieved for the immediately preceding access predicts no memory page crossing;

and

said instruction block selection in said step c) is performed using the second portion of the current physical address of the current access if the predictive annotation retrieved for the immediately preceding access predicts memory page crossing.

6. The method as set forth in claim 1, wherein,

said prior physical address of step (d) is an immediately preceding physical address;

said prior access of step (d) is an immediately preceding access;

said data block selection of step (d) is performed using either the second portion of the current physical address of the current access or the second portion of the immediately preceding physical address of the immediately preceding access, depending on whether the retrieved predictive annotation used for data block selection predicts address page crossing or not; and

said method further comprises the step of (e) latching the second portion of the immediately preceding physical address of the immediately preceding access during the immediately preceding access, said step (e) being performed prior to said steps (c) and (d).

7. The method as set forth in claim 1, wherein,

said prior physical address is a prior physical address of a prior access where a last misprediction occurred;

said prior access is the prior access where the last misprediction occurred;

said data block selection in said step (d) is performed using either the second portion of the current physical address of the current access or the second portion of the prior physical address of the prior access where the last misprediction occurred, depending on whether said retrieved predictive annotation used predicts address page crossing or not; and

said method further comprises the step of (e) latching the second portion of the physical address of the prior access where the last misprediction occurred when the last misprediction was detected, said step (e) being performed prior to said steps (c) and (d).

8. The method as set forth in claim 1, wherein the retrieved predictive annotation used for data block selection is predetermined to be the retrieved predictive annotation of an earlier access, and the earlier access is predetermined to be an access immediately preceding the current access;

and

the method further comprises the step of (e) latching the retrieved predictive annotation of the immediately preceding access during the immediately preceding access, said step (e) being performed before said steps (c) and (d).

9. The method as set forth in claim 1, wherein the retrieved predictive annotation used for data block selection is predetermined to be the retrieved predictive annotation of the current access.

15. The apparatus as set forth in claim 9, wherein,

said prior physical address is an immediately preceding physical address;

said prior access is an immediately preceding access;

said apparatus further comprises

a multiplexor coupled to the selection circuitry for providing either the second portion of the current physical address of the current access or the second portion of the immediately preceding physical address of the immediately preceding access to the selection circuitry, depending on whether the retrieved predictive annotation used for data block selection predicts address page crossing or not; and

a latch coupled to the multiplexor for latching the second portion of the immediately preceding physical address of the immediately preceding access during the immediately preceding access and providing the latched second portion of the immediately preceding physical address of the immediately preceding access to the multiplexor during the current access.

16. The apparatus as set forth in claim 9, wherein,

said prior physical address is a prior physical address of a prior access where a last misprediction occurred;

said prior access is the prior access where the last misprediction occurred;

said apparatus further comprises

a multiplexor coupled to said selection circuitry for providing either the second portion of the current physical address of the current access or the second portion of the prior physical address of the prior access where the last misprediction occurred to said selection circuitry, depending on whether said retrieved predictive annotation used predicts address page crossing or not;

a latch coupled to the multiplexor for latching the second portion of the physical address of the prior access where the last misprediction occurred when the last misprediction was detected, and providing the latched second portion of the physical address of the prior access where the last misprediction occurred to the multiplexor during the current access.

17. The apparatus as set forth in claim 1, wherein the retrieved predictive annotation used for data block selection is predetermined to be the retrieved predictive annotation of an earlier access, and the earlier access is predetermined to be an access immediately preceding the current access;

and

the apparatus further comprises a latch coupled to the third storage unit and multiplexor for latching the retrieved predictive annotation of the immediately preceding access during the immediately preceding access, and outputting the latched predictive, annotation to control the multiplexor during the current access.

18. The apparatus as set forth in claim 1, wherein the retrieved predictive annotation used for data block selection is predetermined to be the retrieved predictive annotation of the current access.

10. In a computer system comprising a first storage unit for storing a data storage structure having a plurality of data vectors, said data storage structure being physically addressed with physical addresses of a physical address space partitioned into a plurality of address pages, and each of said plurality of data vectors having a plurality of data blocks, wherein said first storage unit outputs a currently addressed one of said data vectors during a current access in response to a first portion of a current physical address of the current access, an apparatus for rapidly retrieving data from said physically addressed data storage structure, said apparatus comprising:

a) a second storage unit for storing a plurality of description vectors corresponding to plurality of in a description storage structure, the description storage structure being physically addressed with said physical addresses also, and each of said plurality of description vectors comprising a plurality of descriptors corresponding to said plurality of data blocks, wherein said second storage unit outputs a corresponding one of said plurality of descriptor vectors concurrently with the outputting of the currently addressed data vector by said first storage unit in response to the first portion of the current physical address;

b) a third storage unit for storing a plurality of predictive annotations corresponding to said plurality of data vectors of a predictive annotation storage structure corresponding to said data storage structure, said predictive annotation storage structure being physically addressed with said physical addresses also, and each of said plurality of predictive annotations predicting whether a next access will cross into a new address page, wherein said third storage unit outputs a corresponding one of said plurality of predictive annotations concurrently with the outputting of the currently addressed data vector output by said first storage unit in response to the first portion of the current physical address; and

c) selection circuitry coupled to said first, second and third storage units for selecting a data block from the currently retrieved data vector based on either a second portion of the current physical address of the current access or a second portion of a prior physical address of a prior access, depending on whether a retrieved predictive annotation predicts address page crossing or not, the retrieved predictive annotation being retrieved during either the current or an earlier access, and whether the retrieved predictive annotation of the current access or the retrieved predictive annotation of an earlier access, including which particular earlier access, is to be used for the data block selection is predetermined.

11. The apparatus as set forth in claim 10, wherein, said apparatus further comprises:

d) validation circuitry coupled to said third storage unit for conditionally determining whether the second portions of the current and the prior physical addresses are identical, whenever the retrieved predictive annotation used for data block selection predicts address page crossing, and when said determination is performed, conditionally correcting the predictive annotation in said predictive annotation storage structure from which the retrieved predictive annotation used for data block selection was output, if the determination result is not identical.

12. The apparatus as set forth in claim 10, wherein,

said second and third storage units are the same storage unit storing a merged description and predictive annotation storage structure, said description and said predictive annotation storage structures being logical subsets of said merged description and predictive annotation storage structure;

and

each of said plurality of description vectors and the corresponding predictive annotation are logical subsets of a merged description and predictive annotation vector.

13. The apparatus as set forth in claim 10, wherein,

said physical address space partitioned into a plurality of address pages is a memory space partitioned into a plurality of memory pages;

said data storage structure is a cache array of a n-way set associative instruction cache, where n is an integer greater than or equal to one, said plurality of data vectors being instruction cache lines, said plurality of data blocks being instruction blocks;

said description storage structure is a cache tag array of said n-way set associative instruction cache, said plurality of description vectors being cache tag entries, said plurality of descriptors being address tags with associated control information;

the first and second portions of the physical addresses are lower and higher ordered bits of the physical addresses respectively.

14. The apparatus as set forth in claim 12, wherein,

said selection circuitry selects said instruction block using the second portion of the prior physical address of the prior access if the retrieved predictive annotation used predicts no memory page crossing, and

said selection circuitry selects said instruction block using the second portion of the current physical address of the current access if the retrieved predictive annotation used predicts memory page crossing.