Data processing system and method thereof

• US 5,548,768 A
• Filed: 04/06/1995
• Issued: 08/20/1996
• Est. Priority Date: 03/31/1993
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/419,861
• Time in Patent Office: 502 Days
• Field of Search: 395/375, 395/800
• US Class Current: 712/200
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 : Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A method for executing a data processing instruction in a data processor having a plurality of processing elements, comprising the steps of:

receiving the data processing instruction;

accessing a downward shift value in response to the data processing instruction;

selectively accessing a first data value from a first portion of the plurality of processing elements, the first portion of the plurality of processing elements being determined in response to the downward shift value;

transferring the first data value to each of a second portion of the plurality of processing elements, the second portion of the plurality of processing elements being determined in response to the downward shift value;

performing a data processing operation using the first data value in each of the second portion of the plurality of processing elements; and

storing a result of the data processing operation in each of the second portion of the plurality of processing elements.

2. The method of claim 1 wherein the data processing operation is a mathematical computation which uses both the first data value and one of a plurality of second data values, each of the plurality of second data values being stored in a corresponding one of the plurality of processing elements.

3. The method of claim 1 further comprising the steps of:

accessing a plurality of enable values from a first memory storage circuit, each of the plurality of enable values corresponding to one of the plurality of processing elements; and

selectively enabling each of the second portion of the plurality of processing elements to store the result of the data processing operation in response to a corresponding one of the plurality of enable values.

4. The method of claim 1 wherein the data processing operation is an addition operation in which the first data value is summed with one of a plurality of second data values, each of the plurality of second data values being stored in a corresponding one of the plurality of processing elements.

5. The method of claim 4 further comprising the steps of:

accessing a first extension bit from a second memory storage circuit, the first extension bit providing a status information value;

using the first extension bit during execution of the addition operation; and

selectively modifying the first extension bit to store a modified status information value corresponding to a result of the addition operation.

6. The method of claim 5 wherein the modified status information value indicates when a carry value is generated during execution of the addition operation.

7. The method of claim 5 wherein the data processing instruction is one of a preliminary instruction and a non-preliminary instruction,

the preliminary instruction modifying the first extension bit in response to the result of the addition operation;

and

the non-preliminary instruction modifying the first extension bit to be in a default state.

8. The method of claim 7 wherein the non-preliminary instruction is a saturating instruction and the preliminary instruction is a non-saturating instruction, wherein:

the result of the addition operation is replaced by one of an upper bound and a lower bound when an overflow value corresponding to the result of the addition operation is in an asserted state and the data processing instruction is the non-preliminary instruction; and

the result of the addition operation is not replaced when the overflow value corresponding to the result is in the asserted state and the data processing instruction is the preliminary instruction.

9. The method of claim 8 further comprising the steps of:

negating the first extension bit when the data processing instruction is the non-preliminary instruction; and

selectively modifying the first extension bit in response to execution of the data processing instruction when the data processing instruction is the preliminary instruction.

10. The method of claim 7 wherein the data processing instruction has a mnemonic form of "dadd" when the data processing instruction is the non-preliminary instruction and the data processing instruction has a mnemonic form of "daddp" when the data processing instruction is the preliminary instruction.

11. The method of claim 1 wherein the data processing operation comprises the steps of:

enabling each of the second portion of the plurality of processing elements to compare the first data value to one of a plurality of second data values, each of the plurality of second data values being stored in a corresponding one of the second portion of the plurality of processing elements; and

selectively transferring the first data value to be stored in the corresponding one of the second portion of the plurality of processing elements.

12. The method of claim 11 wherein the result of the data processing operation is one of a greatest value and a least value.

13. The method of claim 11 further comprising the steps of:

accessing a first extension bit and a second extension bit from a storage location, the first extension bit and the second extension bit indicating a previous result of a previous data processing operation executed prior to receipt of the data processing instruction;

using the first extension bit and the second extension bit during execution of the step of enabling each of the second portion of the plurality of processing elements to compare; and

selectively modifying the first extension bit and the second extension bit in response to the data processing operation.

14. The method of claim 13 wherein the first extension bit and the second extension bit collectively represent a plurality of status states, wherein:

the first extension bit and the second extension bit are in a default state in a first status state;

the first extension bit and the second extension bit indicate that the one of the second plurality of data values is less than the first data value when the first extension bit and the second extension bit are in a second status state;

the first extension bit and the second extension bit indicate that the one of the second plurality of data values is greater than the first data value when the first extension bit and the second extension bit are in a third status state; and

the first extension bit and the second extension bit indicate that the one of the second plurality of data values is equal to the first data value when the first extension bit and the second extension bit are in a fourth status state.

15. The method of claim 1 wherein the data processing operation comprises the step of:

selectively storing the first data value in each of the second portion of the plurality of processing elements.

16. The method of claim 15 wherein the data processing instruction has a mnemonic form of "dsrot".

17. The method of claim 15 further comprising the steps of:

accessing a third data value from a third portion of the plurality of processing elements; and

selectively transferring the third data value to each of the first portion of the plurality of processing elements.

18. The method of claim 17 wherein a register is used to indicate one the third portion of the plurality of processing elements which provides the third data value.

19. The method of claim 1 wherein the downward shift value is an operand of the data processing instruction.

20. The method of claim 1 wherein each of the plurality of processing elements corresponds to a processing element number, the processing element number having a binary representation using a plurality of bits, a least significant one of the plurality of bits having a bit position of zero.

21. The method of claim 20 wherein the downward shift value indicates a bit position in the binary representation of the processing element number of each of the plurality of processing elements.

22. The method of claim 21 wherein the first portion of the plurality of processing elements includes each of the plurality of processing elements corresponding to a first plurality of processing element numbers in which a bit position indicated by the downward shift value is negated and a first predetermined value is stored in a plurality of more significant bit positions.

23. The method of claim 22 wherein the second portion of the plurality of processing elements includes each of the plurality of processing elements corresponding to a second plurality of processing element numbers in which the bit position indicated by the downward shift value is asserted and a second predetermined value is stored in a plurality of more significant bit positions.

24. The method of claim 21 wherein the first portion of the plurality of processing elements includes each of the plurality of processing elements corresponding to a first plurality of processing element numbers in which the bit position indicated by the downward shift value is asserted and a first predetermined value is stored in a plurality of more significant bit positions.

25. The method of claim 24 wherein the second portion of the plurality of processing elements includes each of the plurality of processing elements corresponding to a second plurality of processing element numbers in which the bit position indicated by the downward shift value is negated and a second predetermined value is stored in a plurality of more significant bit positions.

26. A data processor, comprising:

an interface circuit for receiving the data processing instruction;

means for accessing a downward shift value in response to the data processing instruction, the means for accessing being coupled to the interface circuit for receiving the data processing instruction;

a plurality of processing elements for storing a plurality of data values;

means for selectively accessing a first data value from a first portion of the plurality of processing elements, the first portion of the plurality of processing elements being determined in response to the downward shift value, the means for selectively accessing being coupled to the plurality of processing elements;

means for transferring the first data value to each of a second portion of the plurality of processing elements, the second portion of the plurality of processing elements being determined in response to the downward shift value, the means for transferring being coupled to the means for selectively accessing;

enable means for enabling each of the second portion of the plurality of processing elements to perform a data processing operation using the first data value, the enable means being coupled to the plurality of processing elements; and

a first storage circuit for storing a result of the data processing operation in each of the second portion of the plurality of processing elements.

27. The data processor of claim 26 wherein the data processing operation is a mathematical computation which uses both the first data value and one of a plurality of second data values, each of the plurality of second data values being stored in a corresponding one of the second portion of the plurality of processing elements.

28. The data processor of claim 26 further comprising:

a second storage circuit for storing a plurality of enable values, each of the plurality of enable values corresponding to one of the plurality of processing elements, each of the plurality of enable values selectively enabling each of the second portion of the plurality of processing elements to store the result of the data processing operation in response to the corresponding one of the plurality of enable values.

29. The data processor of claim 26 wherein the data processing operation is an addition operation in which the first data value is summed with one of a plurality of second data values, each of the plurality of second data values being stored in a corresponding one of the second portion of the plurality of processing elements.

30. The data processor of claim 29 further comprising:

a third memory storage circuit for storing a first extension bit, the first extension bit providing a status information value;

a fourth memory storage circuit for storing a second extension bit, the second extension bit providing a sign value corresponding to the first data value of each of the first portion of the plurality of processing elements; and

a modification means for selectively modifying the first extension bit to store a modified status information value corresponding to a result of the addition operation, the modification means selectively modifying the second extension bit to store a modified sign value corresponding to the sign value of the first data value.

31. The data processor of claim 30 wherein the modified status information value indicates when a carry value is generated during execution of the addition operation.

32. The data processor of claim 30 wherein the data processing instruction is one of a preliminary instruction and a non-preliminary instruction,

the preliminary instruction modifying the first extension bit in response to the result of the addition operation;

and

the non-preliminary instruction modifying the first extension bit to be in a default state.

33. The data processor of claim 26 wherein the result of the data processing operation is one of a greatest value and a least value.

34. The data processor of claim 26 further comprising:

a storage location for storing a first extension bit and a second extension bit, the first extension bit and the second extension bit indicating a previous result of a previous data processing operation executed prior to receipt of the data processing instruction, the first extension bit and the second extension bit being used during execution of the data processing operation.

35. The data processor of claim 34 further comprising:

a modification means for selectively modifying the first extension bit and the second extension bit in response to the data processing operation.

36. The data processor of claim 26 wherein the first data value is copied into each of the second portion of the plurality of processing elements during execution of the data processing operation.

37. The data processor of claim 36 wherein the data processing instruction has a mnemonic form of "dsrot".

38. The data processor of claim 36 wherein the means for selectively accessing accesses a third data value from a third portion of the plurality of processing elements and the means for transferring transfers the third data value to each of the first portion of the plurality of processing elements.

39. The data processor of claim 38 further comprising:

a register for indicating one the third portion of the plurality of processing elements which provides the third data value.

40. The data processor of claim 26 wherein the downward shift value is an operand of the data processing instruction.