Digital parallel processor array for optimum path planning
First Claim
1. A path planning parallel processor, comprising:
- (A) a two dimensional array of processor cells, each of said processor cells comprising;
(1) plural direction input means for receiving stimulus signals from neighboring processor cells along corresponding directions in said array,(2) direction memory means for determining and storing the identity of a direction along which a stimulus signal is first received,(3) means for broadcasting a subsequent stimulus signal to said neighboring processor cells after a locally stored predetermined delay time, wherein said predetermined delay time corresponds to a topology, whereby stimulus signals propagate throughout said array from a starting one of said processor cells;
(B) link means for carrying stimulus signals between neighboring processor cells; and
(C) means for tracing back from a user selected destination one of said processor cells to said starting cell along an optimum path of said processor cells in accordance with said identity of a direction stored in each of said processor cells.
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Abstract
The invention computes the optimum path across a terrain or topology represented by an array of parallel processor cells interconnected between neighboring cells by links extending along different directions to the neighboring cells. Such an array is preferably implemented as a high-speed integrated circuit. The computation of the optimum path is accomplished by, in each cell, receiving stimulus signals from neighboring cells along corresponding directions, determining and storing the identity of a direction along which the first stimulus signal is received, broadcasting a subsequent stimulus signal to the neighboring cells after a predetermined delay time, whereby stimulus signals propagate throughout the array from a starting one of the cells. After propagation of the stimulus signals throughout the array, a master processor traces back from a selected destination cell to the starting cell along an optimum path of the cells in accordance with the identity of the directions stored in each of the cells.
151 Citations
56 Claims
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1. A path planning parallel processor, comprising:
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(A) a two dimensional array of processor cells, each of said processor cells comprising; (1) plural direction input means for receiving stimulus signals from neighboring processor cells along corresponding directions in said array, (2) direction memory means for determining and storing the identity of a direction along which a stimulus signal is first received, (3) means for broadcasting a subsequent stimulus signal to said neighboring processor cells after a locally stored predetermined delay time, wherein said predetermined delay time corresponds to a topology, whereby stimulus signals propagate throughout said array from a starting one of said processor cells; (B) link means for carrying stimulus signals between neighboring processor cells; and (C) means for tracing back from a user selected destination one of said processor cells to said starting cell along an optimum path of said processor cells in accordance with said identity of a direction stored in each of said processor cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method of path planning in an array of parallel processor cells interconnected between neighboring processor cells by link means, comprising:
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(A) in each cell; (1) receiving stimulus signals from neighboring processor cells along corresponding directions in said array, (2) determining and storing the identity of a direction along which a stimulus signal is first received, (3) broadcasting a subsequent stimulus signal to said neighboring processor cells after a predetermined delay time, whereby stimulus signals propagate throughout said array from a starting one of said processor cells; (B) after propagation of said stimulus signals throughout said array, tracing back from a selected destination one of said processor cells to said starting cell along an optimum path of said processor cells in accordance with said identity of a direction stored in each of said processor cells. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. A method of optimum path planning in an array of nodes, neighboring ones of said nodes being linked together so as to enable communication of stimulus signals therebetween, said method comprising:
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programming a pattern of delay times into said array of nodes corresponding to a topology of a terrain to be traversed; electronically traveling all possible paths between a starting one of said nodes and a destination one of said nodes simultaneously, wherein each of said node can only be traveled to once; and sensing which one of said paths provided the minimum travel time from said starting node to said destination node. - View Dependent Claims (42, 43, 44, 45, 46, 47)
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48. A parallel processor for optimum path planning including an array of nodes, neighboring ones of said nodes being linked together so as to enable communication of stimulus signals therebetween, said parallel processor comprising:
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means for programming a pattern of delay times into said array of nodes corresponding to the topology of a terrain to be traversed; means for electronically traveling all possible paths between a starting one of said nodes and a destination one of said nodes; and means for sensing which one of said paths provided the minimum travel time from said starting node to said destination node. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56)
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Specification