Method for forming capped copper electrical interconnects

• US 5,549,808 A
• Filed: 05/12/1995
• Issued: 08/27/1996
• Est. Priority Date: 05/12/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Perfecto, Eric D., White, George E., Kaja, Suryanarayana, Farooq, Mukta S.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Mee, Brendan
• Application Number:
  US08/440,413
• Time in Patent Office: 473 Days
• Field of Search: 205/122, 205/123, 205/125, 205/118, 205/162, 205/178, 205/182, 205/224, 205/917, 437/189, 437/208, 427/443.1
• US Class Current: 205/123
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2203/0597 Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
• CPC Class Codes: H05K 2203/1105 Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
• CPC Class Codes: H05K 3/062 consisting of metals or alloys or metallic inorganic compounds H05K3/065 takes precedence
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: Y10S 205/917 Treatment of workpiece between coating steps

Abstract

The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

Claims

1. A method of making capped electrical interconnect comprising the steps of:

(a) depositing at least one seed layer on a substrate,

(b) depositing at least one resist layer over said at least one seed layer,

(c) exposing and developing said at least one resist layer so as to define at least one opening in said at least one resist layer such that a portion of said at least one seed layer is exposed,

(d) depositing copper in said at least one opening to define electrical interconnects,

(e) thermally treating said substrate through at least one thermal cycle so that said resist separates from said deposited copper, and the side walls of said deposited copper are exposed,

(f) capping said deposited copper electrical interconnect and the side walls thereof with at least one metallic capping material,

(g) removing said at least one resist layer such that at least a portion of said at least one seed layer underneath said at least one resist layer is exposed, and

(h) removing said exposed portion of said at least one seed layer, and thereby forming said capped electrical interconnect.

2. The method of claim 1, wherein said at least one seed layer comprises of at least one first seed layer and at least one second seed layer.

3. The method of claim 2, wherein said at least one first seed layer is selected from a group consisting of chromium, titanium, titanium-tungsten, or alloys thereof.

4. The method of claim 2, wherein said at least one second seed layer is selected from a group consisting of aluminum, copper, or alloys thereof.

5. The method of claim 1, wherein said metallic capping material is selected from a group consisting of aluminum, chromium, cobalt, gold, nickel, palladium, platinum or silver.

6. The method of claim 1, wherein said at least one resist material is conformally deposited.

7. The method of claim 1, wherein said at least one seed layer is at least about 0.05 micron thick.

8. The method of claim 1, wherein the thickness of said deposited copper layer is between about 0.5 micron and about 100.0 micron, and preferably between about 2.0 micron and about 25.0 micron.

9. The method of claim 1, wherein the thickness of said capping layer is between about 0.005 micron and about 10.000 microns, and preferably between about 0.010 micron and about 1.000 microns, and more preferably between about 0.100 micron and about 1.000 microns.

10. The method of claim 1, wherein the temperature of said thermal cycle is preferably between about 50°

C. and about 200°

C., and more preferably about 105°

C.

11. The method of claim 1, wherein at least a portion of said substrate is selected from a group consisting of ceramic substrate or glass ceramic substrate.

12. The method of claim 1, wherein in step (d) said copper is deposited by a method selected from a group consisting of electroless plating or electroplating.

13. The method of claim 1, wherein in step (f) said capping is done by a method selected from a group consisting of electroless plating or electroplating.

14. The method of claim 1, wherein said substrate has at least one internal electrical connection and wherein at least one of said at least one internal electrical connection is electrically connected to said capped electrical interconnect.

15. The method of claim 14, wherein said at least one internal electrical connection is selected from a group consisting of via or internal line.

16. A method of making capped electrical interconnect comprising the steps of:

(a) depositing at least one seed layer on a substrate,

(b) depositing at least one resist layer over said at least one seed layer,

(c) exposing and developing said at least one resist layer so as to define at least one opening in said at least one resist layer such that a portion of said at least one seed layer is exposed,

(d) depositing copper in said at least one opening to define electrical interconnects,

(e) developing said at least one resist layer using at least one heated developer solution so that said at least one resist separates from said deposited copper, and the side walls of said deposited copper are exposed,

(f) capping said deposited copper electrical interconnect and the sidewalls thereof with at least one metallic capping material,

(g) removing said at least one resist layer such that at least a portion of said at least one seed layer underneath said at least one resist layer is exposed, and

(h) removing said exposed portion of said at least one seed layer, and thereby forming said capped electrical interconnect.

17. The method of claim 16, wherein said at least one seed layer comprises of at least one first seed layer and at least one second seed layer.

18. The method of claim 17, wherein said at least one first seed layer is selected from a group consisting of chromium, titanium, titanium-tungsten, or alloys thereof.

19. The method of claim 17, wherein said at least one second seed layer is selected from a group consisting of aluminum, copper, or alloys thereof.

20. The method of claim 16, wherein said metallic capping material is selected from a group consisting of aluminum, chromium, cobalt, gold, nickel, palladium, platinum or silver.

21. The method of claim 16, wherein said at least one resist material is conformally deposited.

22. The method of claim 16, wherein said at least one seed layer is at least about 0.05 micron thick.

23. The method of claim 16, wherein the thickness of said deposited copper layer is between about 0.5 micron and about 100.0 micron, and preferably between about 2.0 micron and about 25.0 micron.

24. The method of claim 16, wherein the thickness of said capping layer is between about 0.005 micron and about 10.000 microns, and preferably between about 0.010 micron and about 1.000 microns, and more preferably between about 0.100 micron and about 1.000 microns.

25. The method of claim 16, wherein the temperature of said thermal cycle is preferably between about 50°

C. and about 200°

C., and more preferably about 105°

C.

26. The method of claim 16, wherein at least a portion of said substrate is selected from a group consisting of ceramic substrate or glass ceramic substrate.

27. The method of claim 16, wherein in step (d) said copper is deposited by a method selected from a group consisting of electroless plating or electroplating.

28. The method of claim 16, wherein in step (f) said capping is done by a method selected from a group consisting of electroless plating or electroplating.

29. The method of claim 16, wherein said substrate has at least one internal electrical connection and wherein at least one of said at least one internal electrical connection is electrically connected to said capped electrical interconnect.

30. The method of claim 29, wherein said at least one internal electrical connection is selected from a group consisting of via or internal line.