Method of fabricating a TFT-EL pixel

• US 5,550,066 A
• Filed: 12/14/1994
• Issued: 08/27/1996
• Est. Priority Date: 12/14/1994
• Status: Expired due to Term

• Current Assignee: Global OLED Technology LLC (LG Display Co., Ltd.)
• Original Assignee: Eastman Kodak Company
• Inventors: Hseih, Biay C., Tang, Ching W.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/355,940
• Time in Patent Office: 622 Days
• Field of Search: 437/40 TF, 437/41 TF, 437/21, 437/913, 437/919, 437/54, 437/59, 148/DIG. 150
• US Class Current: 438/29
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

A method of making a 4-terminal active matrix electroluminescent device that utilizes an organic material as the electroluminescent medium is described. In this method, thin film transistors are formed from polycrystalline silicon at a temperature sufficiently low such that a low temperature, silica-based glass can be used as the substrate.

Claims

1. A method of fabricating a TFT-EL pixel comprising the steps of:

a) providing an insulating substrate having top and bottom surfaces, depositing a layer of silicon on the top surface of said substrate and patterning said layer to form a first and a second polycrystalline silicon island;

b) depositing a first dielectric layer over the top surface of said substrate and over said first and second polycrystalline islands to form a gate dielectric layer;

c) depositing a first strip of material over said first polycrystalline silicon island, and depositing a second strip of material over said second polycrystalline silicon island;

d) depositing a layer for the bottom electrode of a capacitor;

e) ion-implanting into said polycrystalline silicon islands and said strips of material to form source and drain regions and a doped gate electrode;

thus forming first and second thin-film-transistors;

f) depositing a second dielectric layer covering said first dielectric layer, said strips of material, and said bottom layer of a capacitor;

g) etching through said first and second dielectric layers to form source and drain contact holes and depositing conducting material into said source and drain contact holes;

h) depositing a conductive layer that forms the top electrode of said capacitor;

i) depositing a display anode layer electrically connected to said drain of said second thin-film-transistor;

said anode layer disposed on said second dielectric layer;

j) depositing a third dielectric layer over the surface of the article resulting from step i;

k) etching a hole through said third dielectric layer to expose said display anode layer;

l) depositing an organic electroluminescent layer over said display anode layer; and

depositing a cathode layer over said organic layer.

2. The method of claim 1 additionally comprising the steps of depositing a source bus electrically connected to said source region of said first thin-film-transistor;

and depositing a ground bus electrically connected to said capacitor.

3. The method of claim 1 wherein said first strip of material is selected from the group consisting of silicon and a metal silicide, and said second strip of material is silicon.

4. The method of claim 1 wherein said step of etching through said third dielectric layer creates a tapered edge on said third dielectric layer.

5. The method of claim 1 wherein said polycrystalline silicon islands are formed on a low temperature glass substrate by the chemical vapor deposition of an amorphous silicon layer and a low temperature anneal at less than 600°

C., followed by photo lithographically forming islands in a plasma etch.

6. The method of claim 5 wherein said second strip of material and said bottom electrode of said capacitor are formed of a common polysilicon layer that is doped during said ion-implanting step with a dopant selected from the group consisting of Sb, As, P and N.

7. The method of claim 6 wherein said ion-implanting step is followed by dopant activation conducted at about 600°

C.

8. The method of claim 6 wherein said thin-film-transistors are subjected to a hydrogen passivation step in an electron cyclotron resonance plasma system at about 300°

C.

9. The method of claim 1 wherein said organic electroluminescent layer comprises an electron transporting and injecting zone and a hole injecting and transporting zone wherein both zones are deposited by vacuum evaporation.

10. The method of claim 1 wherein said organic electroluminescent layer is about 150 to 200 nm thick.