Method for fabricating a monolithic semiconductor device with integrated surface micromachined structures

• US 5,550,090 A
• Filed: 09/05/1995
• Issued: 08/27/1996
• Est. Priority Date: 09/05/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Shemansky, Frank A. Jr., Ristic, Ljubisa
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Kirkpatrick, Scott
• Application Number:
  US08/523,581
• Time in Patent Office: 357 Days
• Field of Search: 437/901, 437/921, 437/927, 437/228 SEN, 437/ 228 H, 437/228 O, 148/DIG. 159, 148/DIG. 73, 216/11
• US Class Current: 438/52
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence

Abstract

A method for fabricating a monolithic semiconductor device with integrated surface micromachined structures is provided. A semiconductor substrate (10) has an interconnection layer (14) and a first sacrificial layer (16) overlying the substrate (10). Sensor areas (30) and IC areas (40) are formed by patterning the first sacrificial layer (16). A patterned sensor structural layer (32) is formed within sensor area (30) and protected by second sacrificial layer (34) and seal layer (36) while IC elements are formed in IC area (40). Subsequent to IC processing a RTA anneal is performed to relieve stress in sensor layer (32). Sensor area (30) is electrically coupled to IC area (40) and sacrificial layers (16, 34) removed to free sensor elements in sensor areas (40).

Claims

1. A method of manufacturing a monolithic semiconductor device with an integrated surface micromachined structure comprising the steps of:

providing a semiconductor substrate;

forming at least one conductive microstructure, wherein the at least one conductive microstructure overlies said semiconductor substrate within a sensor area, wherein said at least one conductive microstructure is sealed;

forming at least one semiconductor device subsequent to the step of forming said at least one conductive microstructure, wherein said at least one semiconductor device, including conductively doped regions, is formed within an integrated circuit area;

performing a thermal anneal subsequent to the forming of said at least one semiconductor device;

unsealing said at least one conductive microstructure, wherein said at least one conductive microstructure is suspended; and

electrically coupling said at least one conductive microstructure to said at least one semiconductor device.

2. The method of claim 1, wherein the step of providing a semiconductor substrate comprises providing a semiconductor substrate comprising a layer of epitaxial silicon overlying a semiconductor wafer.

3. The method of claim 1, wherein the step of forming at least one conductive microstructure further comprises the prior steps of:

forming an interconnection layer overlying said semiconductor substrate;

forming a first sacrificial layer overlying said interconnection layer, wherein said first sacrificial layer further comprises phosphorus doped silicon dioxide;

forming a structural layer overlying said first sacrificial layer;

forming a second sacrificial layer overlying said structural layer, wherein said second sacrificial layer further comprises phosphorus doped silicon dioxide; and

forming a sealing layer overlying said second sacrificial layer, wherein said sealing layer comprises silicon nitride.

4. The method of claim 3, wherein the step of forming an interconnection layer further comprises forming a material selected from the group of polysilicon, refractory metal silicide and refractory metal salicide.

5. The method of claim 3, wherein the step of forming at least one conductive microstructure further comprises physically and electrically coupling said at least one conductive microstructure to said interconnection layer.

6. The method of claim 5, wherein physically and electrically coupling said at least one conductive microstructure to said interconnection layer further comprises forming anchor openings in said first sacrificial layer.

7. The method of claim 3, wherein the step of forming at least one conductive microstructure further comprises a step of forming an insulating layer underlying said interconnection layer.

8. The method of claim 7, wherein the step of forming said insulating layer comprises forming an insulating layer comprised of silicon nitride, or silicon nitride overlying silicon dioxide.

9. The method of claim 3, wherein the step of forming at least one conductive microstructure further comprises removing said first and second sacrificial layers subsequent to the step of forming at least one semiconductor device.

10. The method of claim 9, wherein the step of forming at least one conductive microstructure comprising removing said first and second sacrificial layers subsequent to the step of forming at least one semiconductor device further comprises depositing and patterning a passivation layer overlying said IC area.

11. The method of claim 3, wherein the step of forming at least one conductive microstructure comprises forming at least one conductive microstructure selected from the group consisting polysilicon and tungsten.

21. The method of claim 11, wherein the step of patterning said structural layer to form at least one sensor structural element comprises forming a microstructure disposed above and electrically coupled to said interconnection layer.

12. A method of fabricating a monolithic semiconductor device with integrated surface micromachined sensor structures comprising the steps of:

providing a semiconductor substrate having a top surface;

forming an interconnection layer overlying said top surface;

forming a first sacrificial layer overlying said interconnection layer;

patterning said first sacrificial layer, wherein an integrated circuit area and a sensor area are defined and wherein selected portions of said first sacrificial layer are removed in said sensor area to form at least one anchor opening exposing said interconnection layer;

forming a structural layer, wherein said structural layer overlies said first sacrificial layer and couples to said interconnection layer through said at least one anchor opening;

patterning said structural layer to form at least one sensor structural element within said sensor area;

forming a second sacrificial layer overlying said sensor area;

forming a sealing layer overlying said sensor area;

then forming semiconductor device structures, including conductively doped regions, within said integrated circuit area;

performing a rapid thermal anneal;

forming a passivation layer overlying said IC area;

removing said sealing layer, first sacrificial layer and said second sacrificial layer, wherein said at least one sensor structural element is suspended; and

electrically coupling said at least one sensor structural element and said semiconductor device structures.

13. The method of claim 12, wherein the step of providing a semiconductor substrate comprises providing a semiconductor substrate comprising a layer of epitaxial silicon overlying a semiconductor wafer.

14. The method of claim 12, further comprising the step of forming an insulating layer, wherein said interconnection layer overlies said insulating layer.

15. The method of claim 14, wherein the step of forming an insulating layer comprises forming a silicon nitride insulating layer.

16. The method of claim 12, wherein the step of forming a passivation layer comprises forming a passivation layer comprising silicon nitride.

17. The method of claim 12, wherein the step of forming a structural layer comprises forming a polysilicon structural layer.

18. The method of claim 17, further comprising the step of doping said layer of polysilicon with phosphorous.

19. The method of claim 12, wherein the step of forming a structural layer comprises forming a tungsten structural layer.

20. The method of claim 12, wherein the step of forming a second sacrificial layer further comprises forming a phosphorus doped silicon dioxide second sacrificial layer.