Apparatus and method for patch recording and recall

• US 5,550,755 A
• Filed: 07/14/1994
• Issued: 08/27/1996
• Est. Priority Date: 07/14/1994
• Status: Expired due to Fees

• Current Assignee: Ian Eales, Martin B. Morgan
• Original Assignee: Ian Eales, Martin B. Morgan
• Inventors: Martin, B. Morgan, Eales, Ian
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/274,963
• Time in Patent Office: 775 Days
• Field of Search: 364/514 R, 364/474.24, 340/825.44, 340/815.47, 340/815.48, 340/815.49, 340/815.5, 340/815.53, 340/815.54, 340/825.21
• US Class Current: 340/815.47
• CPC Class Codes: H01R 13/641 by indicating incorrect coupling; by indicating correct or full engagement
• CPC Class Codes: H01R 2103/00 Two poles
• CPC Class Codes: H01R 24/58 Contacts spaced along longitudinal axis of engagement
• CPC Class Codes: H04H 60/04 Studio equipment; Interconnection of studios
• CPC Class Codes: H04N 5/222 Studio circuitry; Studio devices; Studio equipment cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/268 Signal distribution or switching

Abstract

Patch recording and recall for audio and video consoles is accomplished by detectors uniquely associated with each jack detect the presence of a plug in the associated jack. The connection sensor provides a signal identifying that a connection has been made when a plug is inserted in the jack. A controller receiving the connection signals stores each consecutive connection signal in a memory. Since each connection signal is uniquely identified with a jack in the panel, the stored connection signals are subsequently retrieved by the controller and a patch signal corresponding to the retrieved connection signal indicating a unique jack for the patch to be reconstructed is provided by the controller. Interface with an operator/technician is accomplished through a standard VDU or other appropriate means such as a synthesized voice system.

Claims

1. An apparatus for patch bay interconnection data storage and recall system comprising:

a plurality of light sources located proximate and individually associated with a plurality of jacks in the patch bay;

a plurality of photodetectors individually associated with the plurality of light sources and responsive to impingement of an associated light beam due to insertion of a plug in the associated jack to produce a connection signal;

a controller having

means for receiving the connection signals during a first patch bay setup and storing consecutive connection signals in a memory;

means for retrieving the stored connection signals during a subsequent patch bay setup;

means for providing a patch signal corresponding to a retrieved connection signal; and

means for transmitting patch signals to prompt an operator to make a connection corresponding to the patch signal.

2. An apparatus as defined in claim 1 wherein the means for transmitting patch signals comprises means for blinking a one of the plurality of light sources corresponding to the connection signal.

3. An apparatus as defined in claim 2 wherein the means for transmitting patch signals further comprises a video display and the patch signal includes alphanumeric designation of the jack associated with the defined one of the plurality of light sources for display on the video display.

4. An apparatus as defined in claim 1 wherein the means for transmitting patch signals comprises a voice synthesizer for announcing an alphanumeric designation and the patch signal includes alphanumeric designation of the jack associated with the defined one of the plurality of light sources.

5. An apparatus as defined in claim 1 wherein the plurality of light sources are mounted to a face of a front panel in which the associated jacks are mounted.

6. An apparatus as defined in claim 5 further comprising a designation strip holder mounted to the face of the front panel and wherein the light sources are integral with the designation strip holder.

7. An apparatus as defined in claim 1 wherein each one of the plurality of light sources and each associated one of the photodetectors are mounted on opposite sides of the associated jack and the connection signal is generated responsive to interruption of the light beam between the source and photodetector by insertion of a plug into the jack.

8. An apparatus as defined in claim 1 wherein each one of the plurality of light sources and each associated one of the photodetectors are mounted substantially adjacent to one another proximate the associated jack and the connection signal is generated by reflection of the light beam from a plug inserted in the jack to the photodetector.

9. An apparatus as defined in claim 1 wherein the plurality of light sources and associated photodetectors are segregated into groups such that members of a group are located distal from one another and the means for receiving connection signals samples each group separately, said apparatus further comprising means for illuminating light sources in each group separately and coincident with the sampling of that group by the receiving means.

10. An apparatus as defined in claim 1 wherein the receiving means further comprises means for designating a connection external to the patch bay as one of a pair of consecutive connection signals.

11. An apparatus as defined in claim 1 wherein the receiving means further comprises means for designating a functional identification of a patch.

12. An apparatus as defined in claim 1 wherein the photodetectors each comprise:

a phototransistor; and

an input amplifier having;

a non-inverting amplifier receiving an input from the phototransistors and an output to the receiving means of the controller;

means for low pass filtered feedback on the non-inverting amplifier and means for feedback phase modification on the non-inverting amplifier; and

wherein the system further comprises means for strobing the plurality of light sources at high frequency.

13. An apparatus as defined in claim 6 wherein the light sources comprise light emitting diodes (LEDs) and said designation strip holder incorporates a printed circuit board having notches in the edge thereof each of said notches located adjacent a jack and each notch adapted to receive an LED.

14. An apparatus as defined in claim 13 wherein said notches include angled sides for urging each LED into alignment with the adjacent jack;

said notch further having a bottom with notch wells for receiving solder paste for interconnection of said LED to signal traces on the printed circuit board.

15. An apparatus as defined in claim 6 wherein the photodetectors are integral with the designation strip holder.

16. An apparatus as defined in claim 15 wherein the photodetectors comprise phototransistors and said designation strip holder incorporates a printed circuit board having notches in the edge thereof each of said notches located adjacent a jack and each notch adapted to receive a phototransistor.

17. An apparatus as defined in claim 16 wherein said notches include angled sides for urging the phototransistors into alignment with the adjacent jack;

said notch further having a bottom with notch wells for receiving solder paste for interconnection of said phototransistor to signal traces on the printed circuit board.

18. A method for operation of a patch bay interconnection data storage and recall system which incorporates plug detectors individually associated with a plurality of plug jacks in the patch bay and providing a connection signal upon insertion of a plug, the method comprising the steps of:

receiving the connection signals during a first patch bay setup;

storing consecutive connections signals in a memory;

retrieving the stored connection signals during a subsequent patch bay setup;

providing a patch signal corresponding to a retrieved connection signal; and

transmitting patch signals to prompt the operator to make a connection corresponding to the patch signal.

19. A method as defined in claim 18 further comprising the steps of:

receiving a connection signal for a first one of a consecutive pair of connection signals;

generating an alert responsive to said first one of the connection signals;

receiving a second one of a consecutive of pair of connection signals; and

generating a patch complete notification.

20. A method as defined in claim 18 further comprising the steps of recalling said first one and second one of the consecutive pair of connection signals;

transmitting a first patch signal corresponding to the first one of said retrieved connection signals;

receiving a connection signal corresponding to said first patch signal;

transmitting a second patch signal corresponding to said second one of said retrieved connection signals; and

generating a second alert identifying the second patch signal as completing a patch.

21. A method as defined in claim 18 wherein the plug detectors of the patch bay interconnection data storage and recall system further produce a disconnect signal and the method comprises the additional steps of receiving a disconnect signal corresponding to a previously stored connection signal and generating a third alert signal responsive to receiving the disconnect signal.

22. A method as defined in claim 18 wherein the method further comprises the steps of:

storing jack signal functions;

comparing connection signals to stored jack signal functions to determine incompatible connections; and

generating a fourth alert responsive to a determination of an incompatible connection.

23. A method as defined in claim 22 further comprising the steps of:

storing jack signal functions for at least two patch bays;

comparing received connection signals to said stored jack signal functions;

associating said connection signals to said stored jack signal functions for a first one of said patch bays;

transforming said associated connection signals to said stored jack signal function for a second one of said patch bays; and

providing a patch signal based on the transformed connection signal.

24. A method as defined in claim 20 further comprising the steps of:

detecting disconnection signals;

storing consecutive disconnection signals in the memory;

retrieving the stored disconnection signals;

providing a patch signal corresponding to the retrieved disconnection signals; and

transmitting the patch signals.

25. A method as defined in claim 18 further comprising the steps of:

resequencing the stored connection signals based on patch bay configuration for ordered retrieval;

retrieving the stored connection signals in the resequenced order;

providing patch signals corresponding to the retrieved connection signals; and

transmitting the patch signals.