Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays

• US 5,550,839 A
• Filed: 03/12/1993
• Issued: 08/27/1996
• Est. Priority Date: 03/12/1993
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chu, Jakong J., Buch, Kiran B., Law, Edwin S.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): KEMPER, MELANIE A
• Application Number:
  US08/030,981
• Time in Patent Office: 1,264 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 371/22.1, 371/22.3, 371/22.6, 371/22.2, 395/920, 395/921, 395/923
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays, without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) is preserved by clustering together in the mask-configured integrated circuit (a gate array) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area. Test blocks are inserted in the gate array only where needed, i.e. at the output of any function generator that has connections external to the configurable logic block, and all flip flops are modified to also function as test blocks in a test mode. All logic blocks along asynchronous data paths in the FPGA are timing matched by delay elements in the mask-programmed substitute to preserve timing compatibility to the FPGA.

Claims

1. A method of making and configuring a mask-configured logic cell array configured to emulate the logical operations of a user-configured logic cell array during normal mode operations, comprising the steps of:

providing a netlist describing the configuration of the user-configured logic cell array, the netlist including a plurality of logic blocks each including a plurality of logic gates present on the user-configured logic cell array; and

configuring the mask-configured logic cell array according to the netlist without a logic simulation to verifying functionality of the configured mask-configured logic cell array, the mask configured logic cell array including a plurality of logic gate clusters placed and routed to correspond one-to-one to used logic blocks of the user-configured logic cell array, each cluster being a plurality of logic gates having physical proximity, but not including at least some logic gate clusters corresponding to unused logic blocks on the user configured logic cell array.

2. The method of claim 1, wherein the logic blocks each include at least one function generator and further comprising the steps of:

providing a plurality of test blocks on the mask configured logic cell array; and

connecting a test block to each function generator in a logic block only if an output signal line of the function generator is directly connected externally to the logic block.

3. The method of claim 1, further comprising the step of connecting multiplexers to each of a clock and data input terminal of a plurality of flip-flops present on the mask-configured logic cell array, thereby providing a test capability for each such flip flop.

4. The method of claim 1, wherein no timing simulation of the netlist is required to ensure functionality of the mask-configured logic cell array.

5. The method of claim 1, wherein no logic simulation of the netlist is required to ensure functionality of the mask-configured logic cell array.

6. The method of claim 1, further comprising the steps of:

providing test elements in the logic cell array, the logic blocks having a plurality of logic function generators and each logic function generator being a collection of logic gates forming a look up table for implementing a specific logic function;

determining for each logic function generator if it has an output terminal connected to provide an output signal outside of the logic block of which the logic function generator is a part;

providing a test element associated with each logic function generator so connected, and not providing a test element for other logic function generators;

connecting the test element to the output terminal of the associated function generator; and

connecting together a plurality of the test elements.

7. A mask-configured integrated circuit chip in its configured state to be substituted for a user-configured integrated circuit chip, the mask-configured integrated circuit chip in its configured state being pin compatible with the user configured integrated circuit chip, and comprising:

a plurality of configured mask-configured routing lines for routing signals previously routed by pass transistors and line segments of the user-configured integrated circuit chip; and

a plurality of cluster groups of logic elements, each cluster group of elements corresponding to a user-configured logic block in the user-configured integrated circuit chip,

wherein the functions of each logic block in the user-configured integrated circuit chip are carried out in a corresponding configured clustered group of logic elements in the mask-configured integrated circuit, each gate in each clustered group being placed and routed to have physical proximity to all other gates in the clustered group, and at least one unused logic gate in a logic block of the user-configured integrated circuit chip not being replicated in the corresponding clustered group.

8. The mask-configured integrated circuit chip of claim 7, wherein each cluster group comprises at least one function generator and further comprises a test logic block connected to an output line of the function generator only if an output line of the function generator is connected externally to the logic block.

9. The mask configured integrated circuit chip of claim 8, in which each of the cluster groups further includes a flip flop having clock and data input terminals, each clock and data input terminal being driven by a multiplexer.

10. The mask configured integrated circuit chip of claim 7, wherein the clustered groups of elements are of non-uniform physical dimensions.

11. The mask configured integrated circuit chip of claim 7, wherein the clustered groups of elements have differing numbers of logic gates one to another.

12. The mask configured integrated circuit chip of claim 8, further including an on-chip test capability comprising:

a plurality of logic function generators in the logic blocks, each logic function generator having a collection of logic gates forming a look up table for implementing a specific logic function; and

a plurality of test elements, each test element being associated with one of the logic function generators which has an output terminal connected to provide an output signal outside a particular logic block, wherein each test element is connected to the output terminal of the associated logic function generator.