Condition decision circuit for a microcomputer

• US 5,550,994 A
• Filed: 05/23/1994
• Issued: 08/27/1996
• Est. Priority Date: 06/14/1993
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tashiro, Tetsu, Cho, Yoshiki
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/247,836
• Time in Patent Office: 827 Days
• Field of Search: 395/375, 395/775, 395/800
• US Class Current: 712/236
• CPC Class Codes: G06F 9/322 for non-sequential address
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A high-speed microcomputer having a condition decision circuit in which a signal output indicating whether or not a branch condition is satisfied is always active by taking out only a necessary bit by a mask register value after comparing a register value and a compare register value for every bit.

Claims

1. A microcomputer, comprising:

a condition decision circuit, having;

a register group including a plurality of registers, one of which is specified by execution of a conditional branch instruction, and to which a predetermined value in the code of said conditional branch instructions is set;

a comparing register which stores the operation result of the instruction execution;

compare means for comparing a value of the register specified by the conditional branch instruction in said registers group and a value of said compare register bit by bit; and

a mask register which, by masking values of only necessary bits of the register specified by the conditional branch instruction in said register group, forces a condition decision signal, representing whether or not the branch condition of the conditional branch instruction is satisfied, to a state representing that the branch condition is satisfied.

2. A microcomputer as set forth in claim 1, wherein said condition decision circuit executes specifying the register, specifying bits to be compared, and discriminating signal values.

3. A microcomputer as set forth in claim 1, wherein

the plurality of registers of the register group are designated as condition decision targets of said condition decision circuit, said register group being utilized for controlling a peripheral functional circuit, operation result flags and an interruption request bit group.

4. A microcomputer as set forth in claim 1, comprising:

means (106) for synchronizing said condition decision signal with a basic clock.

5. A microcomputer as set forth in claim 1, wherein an unconditional branch is executed by providing a 1-bit control code, via the instruction code, directly to said condition decision circuit.