Low cost writethrough cache coherency apparatus and method for computer systems without a cache supporting bus

• US 5,551,006 A
• Filed: 09/30/1993
• Issued: 08/27/1996
• Est. Priority Date: 09/30/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kulkarni, Upendra M.
• Primary Examiner(s): Robertson, David L.
• Assistant Examiner(s): Tran, Denise
• Application Number:
  US08/130,025
• Time in Patent Office: 1,062 Days
• Field of Search: 395/823, 395/842, 395/843, 395/868, 395/462, 395/468, 395/489, 395/473
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)

Abstract

An apparatus and method for supporting a writethrough cache in a computer system not otherwise supporting cache is disclosed. Cache coherency is guaranteed by a cache coherency module detecting the CPU programming a DMA controller to allow a device other than the CPU to transfer data to main memory and, until the data transfer is concluded, flushing the cache each time the CPU reads an address other than an address of a standard computer system component. The cache is also flushed upon conclusion of the data transfer. In computer systems including a bus master device, the cache is flushed whenever the cache coherency module detects the CPU reading an address other than an address of a standard computer system component and whenever the cache coherency module detects an interrupt other than a standard computer system interrupt. The cache coherency module includes a bus snooping sub-module to snoop address, control and data on the bus; a DMA address table and a system address table to define DMA addresses, standard system component addresses and standard system interrupts; and a control logic sub-module to identify DMA programming actions, non-standard addresses and non-standard interrupts, and to issue cache flush signals. Also disclosed is an apparatus and method to automatically determine the range of cacheable addresses in the computer system and to turn on the cache after the computer system is reset.

Claims

1. A writethrough cache coherency module for a computer system wherein said computer system includes a bus a CPU connected to said bus, a cache memory connected to said CPU, a main memory connected to said bus, and a DMA controller connected to said bus, said cache coherency module comprising:

a. a bus snooping sub-module connected to said bus for detecting address, control and data signals on said bus;

b. a DMA address table defining the addresses of registers of said DMA controller;

c. a system address table defining standard I/O addresses;

d. a control logic sub-module connected to said cache memory and said bus snooping sub-module and communicating with said DMA address table and said system address table, said control logic sub-module comparing addresses detected by said bus snooping module with the addresses defined by said DMA address table and said system address table to;

(1) detect a memory write period during which said DMA controller is programmed to allow a device other than said CPU to write to main memory;

(2) flush said cache memory when an I/O address other than a standard I/O address defined by said system address table is read by said CPU during said memory write period; and

(3) flush said cache memory at the end of said memory write period.

2. The cache coherency module of claim 1 wherein said system address table further defines standard interrupts, and wherein said cache coherency module detects a bus master device in said computer system and thereafter flushes said cache memory whenever said CPU reads an I/O address other than a standard I/O address defined by said system address table and whenever said bus snooping module detects an interrupt other than a standard interrupt defined by said system address table.

3. The cache coherency module of claim 1 wherein said system address table further defines addresses of a battery backup memory and a keyboard port and wherein said control logic sub-module detects access by said CPU to said battery backup memory or said keyboard port and interprets said access as either a warm reset or a cold reset, said control logic sub-module turning on said cache memory immediately in response to said warm reset and after a computer system self test has run in response to said cold reset.

4. The cache coherency module of claim 3 wherein said cold reset is indicated by a 0 on bit 2 of said keyboard port or by data 00h through 04h at location 0Fh in said battery backup memory, and a warm reset is indicated by a 1 at bit 2 of said keyboard port or by data 05h through 08h at location 0F in said battery backup memory.

5. The cache coherency module of claim 3 wherein said cache memory is turned on in case of a cold reset immediately after said cache coherency module detects software interrupt 19h.

6. The cache coherency module of claim 1 wherein said system address table contains a battery backup memory address lookup table containing addresses in memory giving the configuration of installed conventional memory and extended memory.

7. The cache coherency module of claim 6 wherein said said addresses in memory giving the configuration of installed conventional memory and extended memory are I/O addresses 0070h and 0071h.

8. The cache coherency module of claim 2 wherein said DMA controller has DMA channels one through four each capable of operating in either a normal mode or a cascade mode and wherein said cache coherency module recognizes the presence of a bus master device in said system by detecting that one of said DMA channels other than channel four is programmed to operate in said cascade mode.

9. The cache coherency module of claim 2 wherein said cache coherency module detects that said computer system is a MCA computer system and detects the presence of a bus master device in said MCA computer system and thereafter flushes said cache memory whenever said CPU reads an I/O address other than a standard I/O address defined by said system address table and whenever said bus snooping module detects an interrupt other than a standard interrupt defined by said system address table.

10. The cache coherency module of claim 9 wherein said DMA controller has DMA channels one through four each capable of operating in either a normal mode or a cascade mode and wherein detecting that said computer system is a MCA system includes detecting that channel four of said DMA controller is not programmed for cascade mode.

11. The cache coherency module of claim 1 further comprising logic determining a range of cacheable memory.

12. The cache coherency module of claim 11 further comprising logic turning on said cache after a reset.

13. A writethrough cache coherency module for a computer system wherein said computer system includes a bus, a CPU connected to said bus, a cache memory connected to said CPU, a main memory connected to said bus, a plurality of addressable devices some portion of which have standard addresses, a DMA controller connected to said bus, at least one external I/O device connected through said DMA controller to said bus, a plurality of additional addressable devices in said computer system each connected to said bus and having either a standard or non-standard address, said cache coherency module comprising:

monitoring means connected to said bus for monitoring signals on said bus;

storage means including the addresses of all standard address devices in said computer system;

logic means connected to said monitoring means and said memory means and to said cache memory for determining the period of time during which said external device is writing to main memory and for supplying a cache flush signal to said cache memory upon the completion of said period of time during which said external device is writing to main memory.

14. The cache coherency module of claim 13 wherein said storage means for storage of the addresses of all standard address devices is a look up table.

15. The cache coherency module of claim 13 wherein said storage means includes the addresses of all programmable registers and status registers of said DMA controller.

16. The cache coherency module of claim 13 wherein said means for determining the period of time during which said external device is writing to main memory includes:

means for determining when said DMA controller is programmed to allow an addressable device to write to main memory;

means for determining when said DMA controller is no longer programmed to allow said addressable device to write to main memory; and

means for detecting reads made by said CPU to devices with non-standard addresses.

17. The cache coherency module of claim 16 wherein said means for determining when said DMA controller is no longer programmed to allow said addressable device to write to main memory includes means for interrogating a DMA status register on each hardware interrupt.

18. The cache coherency module of claim 17 wherein said means for interrogating said DMA status register includes:

storage means for storing the data in said DMA status register upon each interrogation; and

logic for causing a logical OR with the data in said storage means and with the data in said DMA status register and supplying the result thereof to said CPU.

19. A method to maintain cache coherency in a computer system, the method comprising the steps of a cache coherency module:

(a) detecting a CPU programming a DMA controller to transfer data to a main memory;

(b) detecting conclusion of the data transfer and flushing a cache coupled to the CPU in response;

(c) detecting the CPU reading a non-standard address during the time interval between steps (a) and (b) and flushing the cache in response.

20. The method of claim 19 wherein said step of a cache coherency module detecting a CPU programming a DMA controller comprises the steps of the cache coherency module:

(a1) snooping addresses asserted by the CPU onto a bus intercoupling the CPU, DMA controller and cache coherency module; and

(a2) comparing the addresses against a table defining addresses of registers of the DMA controller.

21. The method of claim 19 wherein said step of a cache coherency module detecting a CPU programming a DMA controller comprises the step of the cache coherency module snooping a bus intercoupling the CPU, DMA controller and cache coherency module to detect the CPU unmasking a channel of the DMA controller, programming a mode register of the DMA controller, and enabling a global enable/disable bit of the DMA controller.

22. The method of claim 19 wherein said step of a cache coherency module detecting conclusion of the data transfer comprises the steps of the cache coherency module detecting completion of the data transfer.

23. The method of claim 22 wherein said step of the cache coherency module detecting completion of the data transfer comprises the steps of:

(b1) the CPU periodically reading a value from a status register in the DMA controller via a bus intercoupling the CPU, DMA controller and cache coherency module; and

(b2) the cache coherency module snooping the bus to detect the value, the value indicating whether the data transfer is complete.

24. The method of claim 19 wherein said step of a cache coherency module detecting conclusion of the data transfer comprises the step of the cache coherency module detecting the CPU programming the DMA controller to perform an operation other than a write to the main memory.

25. The method of claim 19 wherein said step of a cache coherency module detecting conclusion of the data transfer comprises the steps of:

the CPU

(b1) reading a value from a status register in the DMA controller via a bus intercoupling the CPU, DMA controller and cache coherency module, said step of reading performed in response to a system timer interrupt, and said step of reading destroying the contents of the status register; and

the cache coherency module

(b2) snooping the bus to detect the value, the value indicating whether the data transfer is complete;

(b3) storing a local copy of the value; and

(b4) detecting a read from the status register in the DMA controller in response to an event other than the system timer interrupt and logically ORing data on the bus from the status register with the local copy.

26. The method of claim 19 wherein said step of detecting a CPU programming a DMA controller to transfer data to a main memory comprises the step of reading a status register of the DMA controller to clear any stale status bits therein.

27. The method of claim 19 wherein said step of detecting the CPU reading a non-standard address comprises the steps of the cache coherency module:

(c1) snooping an address asserted by the CPU onto a bus intercoupling the CPU and cache coherency module; and

(c2) comparing the address asserted by the CPU against a table defining standard addresses.

28. A method to maintain cache coherency in a computer system having a bus intercoupling a CPU and cache coherency module, the method comprising the steps of the cache coherency module:

(a) detecting a bus master coupled to the bus;

(b) detecting the CPU reading a non-standard address and flushing a cache coupled to the CPU in response; and

(c) detecting a non-standard interrupt and flushing the cache in response thereto.

29. The method of claim 28 wherein said step of detecting a bus master coupled to the bus comprises the steps of the cache coherency module:

(a1) detecting channel four of the DMA controller programmed in cascade mode; and

(a2) detecting another channel of the DMA controller programmed in cascade mode.

30. The method of claim 28 wherein said step of detecting a bus master coupled to the bus comprises the steps of:

(a1) the cache coherency module detecting channel four of the DMA controller programmed in a mode other than cascade mode; and

(a2) a software utility examining card configuration data files.

31. The method of claim 28 wherein said step of detecting the CPU reading a non-standard address comprises the steps of the cache coherency module:

(b1) snooping an address asserted onto the bus by the CPU; and

(b2) comparing the address against a table defining standard addresses.

32. The method of claim 28 wherein said step of detecting a non-standard interrupt comprises the steps of the cache coherency module:

(c1) snooping an interrupt asserted on the bus; and

(c2) comparing the interrupt against a table defining standard interrupts.