Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program

• US 5,551,033 A
• Filed: 06/04/1992
• Issued: 08/27/1996
• Est. Priority Date: 05/17/1991
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: Zenith Data Systems Corp. (Acer, Inc.)
• Inventors: Foster, Mark J., Walker, James L., Belt, Steven L., Mendelow, Matthew B., Sun, Jiming, Willoughby, Brian D., Brahman, Rodman S., Maddix, Michael D., Fakhruddin, Saifuddin T., Hovey, Scott A., Krau, Michael P., Ruthenbeck, Mark A.
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): Banankhah, Majid A.
• Application Number:
  US07/893,432
• Time in Patent Office: 1,545 Days
• Field of Search: 395/650, 395/734, 364/200, 364/DIG. 1, 364/DIG. 2, 364/231, 364/240, 364/246
• US Class Current: 713/100
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 9/463 Program control block organisation
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.

Claims

1. An apparatus comprising:

a processor having an interrupt input, first and second mask registers controlled by said processor and each having a bit indicating whether an interrupt signal present at said interrupt input is to be enabled or disabled, first means responsive to said interrupt input and said bit in said first mask register for respectively permitting and obstructing recognition of said interrupt signal by said processor when said bit of said first mask register is respectively indicating that said interrupt signal is respectively enabled and disabled, second means responsive to said interrupt input and said bit in said second mask register for respectively permitting and obstructing recognition of said interrupt signal by a further circuit when said bit of said second mask register is respectively indicating that said interrupt signal is respectively enabled and disabled, and means responsive to loading of said first mask register by said processor for conforming said bit of said second mask register to said bit of said first mask register.

2. An apparatus according to claim 1, wherein said processor has first and second operational modes, wherein in said first operational mode said processor has a predetermined set of operational capabilities and in said second operational mode said processor can perform a first subset of said operational capabilities and is inhibited from performing a second subset of said operational capabilities different from said first subset, and wherein said means responsive to loading of said first mask register by said processor includes means for saving information from said processor, for thereafter forcing said processor to said first operational mode, for then conforming said bit of said second mask register to said bit of said first mask register, and for thereafter restoring to said processor said information saved therefrom to cause said processor to return to and resume operation in the operational mode which said processor was in immediately before said saving of said information.

3. An apparatus according to claim 2, wherein said first operational mode is a real mode, and said second operational mode is a protected mode.

4. An apparatus, comprising:

a processor having first and second operational modes, wherein in said first operational mode said processor has a predetermined set of operational capabilities and in said second operational mode said processor can perform a first subset of said operational capabilities and is inhibited from performing a second subset of said operational capabilities different from said first subset;

first and second registers which can each be loaded by said processor; and

control means responsive to a load of said first register by said processor during execution of a program in said second operational mode for interrupting execution of the program in a manner invisible to the program, for thereafter causing said processor to conform said second register to said first register, and for thereafter resuming execution of the program in said second operational mode in a manner invisible to the program.

5. An apparatus according to claim 4, wherein said processor has an interrupt input, wherein said first and second registers are each a mask register having a bit indicating whether an interrupt signal present at said interrupt input is to be enabled or disabled, first means responsive to said interrupt input and said bit in said first register for respectively permitting and obstructing recognition of said interrupt signal by said processor when said bit of said first register is respectively indicating that said interrupt signal is respectively enabled and disabled, and second means responsive to said interrupt input and said bit in said second register for respectively permitting and obstructing recognition of said interrupt signal by a further circuit when said bit of said second register is respectively indicating that said interrupt signal is respectively enabled and disabled.

6. An apparatus according to claim 4, wherein said control means includes said processor having a non-maskable interrupt input, includes means for activating an interrupt signal at said interrupt input in response to a load of said first register, and includes means responsive to activation of said interrupt signal at said interrupt input for saving information from said processor, for forcing said processor to said first operational mode, for thereafter causing said processor to execute in said first operational mode an interrupt routine which effects said conforming of said second register to said first register, and for thereafter restoring to said processor said information saved therefrom in order to cause said processor to resume execution of said program in said second operational mode.

7. An apparatus according to claim 6, wherein said first operational mode is a real mode, and said second operational mode is a protected mode.

8. A method of operating an apparatus which includes a processor having an interrupt input, and first and second mask registers controlled by said processor and each having a bit indicating whether an interrupt signal present at said interrupt input is to be enabled or disabled, comprising the steps of:

respectively permitting and obstructing recognition of said interrupt signal by said processor when said bit of said first mask register is respectively indicating that said interrupt signal is respectively enabled and disabled;

respectively permitting and obstructing recognition of said interrupt signal by a further circuit when said bit of said second mask register is respectively indicating that said interrupt signal is respectively enabled and disabled; and

responding to a load of said first mask register by conforming said bit of said second mask register to said bit of said first mask register.

9. A method according to claim 8, wherein said processor has first and second operational modes, wherein in said first operational mode said processor has a predetermined set of operational capabilities and in said second operational mode said processor can perform a first subset of said operational capabilities and is inhibited from performing a second subset of said operational capabilities different from said first subset, and wherein said responding step includes the steps of saving information from said processor, forcing said processor to said first operational mode, thereafter conforming said bit of said second mask register to said bit of said first mask register, and thereafter restoring to said processor said information saved therefrom to cause said processor to return to and resume operation in the operational mode which was in effect immediately before said saving step.