Method and apparatus for communication variable length messages between register modeled radio devices

• US 5,551,068 A
• Filed: 05/12/1994
• Issued: 08/27/1996
• Est. Priority Date: 05/28/1992
• Status: Expired due to Term

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bane, Ronald L., Klingberg, Jeffrey W., Goldsmith, Eric S., Ehmann, Charles M.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): LE, THANH C
• Application Number:
  US08/241,951
• Time in Patent Office: 838 Days
• Field of Search: 455/89, 370/85.1, 370/85.3, 370/94.1, 370/95.1, 370/95.3, 375/222, 375/223, 375/377, 364/900
• US Class Current: 370/466
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving

Abstract

A radio system (100) includes a plurality of addressable processors (150, 180, and 200). A communication link (230) interconnects the addressable processors (150, 180, and 200). The communication between the addressable processors is conducted via a first and a second communication protocols. The first communication protocol includes a plurality of fixed length information packets for passing parametric data to or from the addressable processors at a fixed baud rate including a packet for changing the communication protocol. The second communication protocol includes a plurality of variable length information packets for passing parametric data to or from the addressable processors at selectable speeds. Whereby the operating state of the addressable processors may be determined or altered by, respectively, communicating parametric data from or to the addressable processor at variable baud rates.

Claims

1. A radio system, comprising:

a communication device having at least one addressable processor means;

at least one additional addressable processor means;

a communication means, comprising a serial communication link, for interconnecting the at least one and the at least one additional addressable processor means, the communication means includes a signal line and a busy line;

a first communication protocol including a plurality of information packets for passing parametric data between the at least one and the at least one additional addressable processor means, the first communication protocol further including a first information packet for changing the communication protocol and changing the baud rate to a baud rate chosen from among a plurality of baud rates; and

a second communication protocol including a second plurality of information packets for passing parametric data to or from the addressable processor means at selectable speeds, the second plurality of information packets include information on the length of a second information packet that will immediately follow the first information packet, the second communication protocol further including the second information packet which has an uninterrupted variable length;

whereby the operating state of the addressable processor means is determined or altered by, respectively, communicating parametric data between the at least one and the at least one additional addressable processor means.

2. The radio system of claim 1, wherein the first and second information packets include:

a variable length operation code;

a variable length message size packet optional data; and

optional error detection data.

3. The radio system of claim 2, wherein the first and second information packets further comprise an address.

4. The radio system of claim 1, wherein the second communication protocol includes at least one of the information packets of the first communication protocol.

5. The radio system of claim 1, wherein the variable operation code includes one or more codes selected from the group of codes consisting of reset operation code, read operation code, write operation code, bit set operation code, bit clear operation code, acknowledge operation code, and negative acknowledge operation code.

6. The radio system of claim 4 wherein the optional error detection includes a cyclic redundancy check packet.

7. The radio system of claim 4 wherein the optional error detection data includes a check sum packet.

8. A register-modeled radio device, comprising:

a communication device having at least one register-modeled processor means;

at least one additional register-modeled processor means;

a serial communication link including a signal line and a busy line for coupling and providing communication between the at least one register-modeled processor means and the at least one additional register-modeled processor means;

a fixed baud rate communication protocol for passing parametric data between the at least one and the at least one additional register-modeled processor means, the communication protocol comprising an information packet for establishing communication between at least one and the at least one additional register-modeled processor means at a selectable baud rate, the information packet further comprising;

information for changing the communication protocol between the at least one and the at least one additional register-modeled processor means;

optional information for preventing other register-modeled processor means from interfering with the communication between the at least one and the at least one additional register-modeled processor means;

a selectable baud rate communication protocol for communicating information to or from the at least one and the at least one additional register-modeled processor means using the serial communication link, the selectable baud rate communication protocol comprising;

an uninterrupted variable length operational code selected from the group of codes consisting of reset operation code, read operation code, write operation code, bit set operation code, bit clear operation code, acknowledge operation code, negative acknowledge operation code; and

a variable length size identifier code;

whereby the virtual state of the at least one and the at least one additional register-modeled processor means is determined or altered, respectively, by communicating information between at least one and the at least one additional the register-modeled processor means.

9. The register-modeled radio communication device of claim 8, wherein the selectable baud rate communication protocol further comprises at least one data packet.

10. The register-modeled radio communication device of claim 8, wherein the selectable baud rate communication protocol further comprises at least one error detection packet.

11. In a radio communication system having a plurality of addressable register means, a method of communicating between the plurality of addressable register means comprising the steps of:

generating, in a first addressable register means of a communication device, a fixed length information packet having at least a protocol switch operation code, an address, and an error detection code;

activating, in the first addressable register means, a hardware busy line to prevent other addressable components from interfering in the communication between the first and a second addressable register means;

transmitting, the fixed length information packet to the second addressable register means using a fixed baud rate communication protocol over a serial communication link;

receiving, at the second addressable register means, the fixed length information packet from the serial communication link;

switching the communication protocol at the first and the second addressable register means to a selectable baud rate communication protocol in response to the contents of the protocol switch operation code;

communicating uninterrupted variable length information packets between the first and the second addressable register means using the selectable baud rate communication protocol; and

releasing, in the first addressable register means, the hardware busy line to force the first and the second register means to revert back to the first communication protocol and to allow the plurality of addressable register means to communicate to each other.

12. In a radio communication system having a plurality of addressable register means, a method of communicating between the plurality of addressable register means comprising the steps of:

generating, in a first register means, an information packet having baud rate change information and an error detection code;

activating, in the first addressable register means, a hardware busy line to prevent other addressable components from interfering in the communication between the first and a second addressable register means;

transmitting, the information packet to a communication device having a second register means using a first baud rate communication protocol over a serial communication link;

receiving, at the second register means, the information packet from the serial communication link;

switching the baud rate at the first and the second register means to a second baud rate in response to the baud rate change information which is contained in the information packet;

communicating uninterrupted variable length information packets between the first and the second addressable register means using the second baud rate; and

releasing, in the first addressable register means, the hardware busy line to force the first and the second addressable register means to revert back to the first communication protocol and to allow the plurality of addressable register means to communicate to each other.

13. The method of claim 12, further including the step of performing the operation designated by the variable length information packet.

14. In a radio communication system having a plurality of addressable components, a method of communicating between the plurality of addressable devices using a plurality of modes comprising the steps of:

generating, in a first addressable component, a first information packet using a first mode having at least a first operation code, an address, and a fixed length argument;

activating, in the first addressable component, a hardware busy line to prevent other addressable components from interfering in the communication between the first and the second addressable components;

transmitting, serially, the first information packet to a communication device having a second addressable component over a serial communication link;

receiving, serially at the second addressable component, the first information packet from the serial communication link;

switching at the first and the second addressable components to a second mode based on the contents of the first information packet;

generating, in the first addressable component, a second information packet using the second mode having at least a second operation code, and an uninterrupted variable length argument;

transmitting, serially, the second information packet to the second addressable component over a serial communication link;

receiving, serially at the second addressable component, the second information packet from the serial communication link; and

performing at the second addressable component the operation designated by the second operation code;

releasing, in the first addressable component, the hardware busy line to force the first and the second addressable components to revert back to the first mode and to allow the plurality of addressable components to communicate to each other.

15. The method of claim 14, further including the step of communicating additional packets between the first and the second addressable components using the second mode.

16. The method of claim 15, wherein the step of generating the second information packet includes generating an information packet having a plurality of sub-packets having at least one checksum sub-packet.

17. The method of claim 16, wherein the step of generating the second information packet includes the step of ensuring that the time between the transmission of the sub-packets does not exceed a pre-determined time interval.

18. The method of claim 17, further including the step of sending, from the second addressable component, a negative acknowledge when the time between the transmission of the sub-packets exceeds the pre-determined time interval.

19. The method of claim 18, further including the step of sending, from the second addressable component, a negative acknowledge when an error was detected based on the checksum sub-packet.

20. The method of claim 19, further including the step of retransmitting, in the first addressable component, the additional information packets.

21. A method of programming a radio communication device using a programming device, comprising the steps of:

generating, in the programming device, a fixed length information packet having at least a protocol switch operation code and an error detection code;

activating, in the programming device, a hardware busy line to prevent other addressable components from interfering in the communication between the programming device and the radio communication device;

transmitting, the fixed length information packet to the radio communication device using a fixed baud rate communication protocol over a serial communication link;

receiving, at the radio communication device, the fixed length information packet from the serial communication link;

switching at the programming device and the radio communication device to an uninterrupted variable length and selectable baud rate communication protocol in response to the information contained in the fixed length information packet;

transmitting programming information from the programming device to the radio communication device using the second communication protocol; and

programming the radio communication device using variable length information packets transmitted by the programming device; and

releasing, in the programming device, the hardware busy line to force the programming device and the radio communication device to revert back to the first communication protocol and to allow the programming device and the radio communication device to communicate to each other.

22. A method of programming a radio communication device using a programming device, comprising the steps of:

generating, in the programming device, a first information packet having at least a protocol switch operation code and an error detection code;

activating, in the programming device, a hardware busy line to prevent other addressable components from interfering in the communication between the programming device and the radio communication device;

transmitting, the first information packet to the radio communication device using a first communication protocol having a first baud rate over a serial communication link;

receiving, at the radio communication device, the first information packet from the serial communication link;

switching at the programming device and the radio communication device to a second communication protocol in response to the information conveyed by the first information packet, the second communication protocol using an uninterrupted variable length message block; and

transmitting programming information from the programming device to the radio communication device using the second communication protocol; and

programming the radio communication device; and

releasing, in the programming device, the hardware busy line to force the first and the radio communication device to revert back to the first communication protocol and to allow the programming device and the radio communication device to communicate to each other.