Circuit and method of series biasing a single-ended mixer

• US 5,551,076 A
• Filed: 09/06/1994
• Issued: 08/27/1996
• Est. Priority Date: 09/06/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bonn, Fred H.
• Primary Examiner(s): Faile, Andrew I.
• Application Number:
  US08/300,768
• Time in Patent Office: 721 Days
• Field of Search: 327/552, 327/559, 327/408, 327/404, 327/416, 327/113, 327/356, 455/118, 455/313, 455/323, 455/326, 455/332, 455/333
• US Class Current: 455/333
• CPC Class Codes: H03D 7/125 with field effect transistors

Abstract

A mixer circuit (10) combines a buffered RF signal with the LO signal at the gate of a mixing transistor (20) for providing sum and difference product terms as the IF output signal. An inductor (46) provides a DC signal path between the source of the mixing transistor and the drain of the buffering transistor (14) to share the same operating current and thereby reduce power consumption in the mixer. The DC path inductor provides a high impedance to block the RF signal and LO signal. A bias circuit (26, 28) sets the bias point at the gate of the mixing transistor to a mid-point value between V_DD and ground potential. In disable mode, the bias point of the mixing transistor is sufficiently low that the LO signal does not have sufficient power to turn on buffering and mixing transistors that could generate mixing products at the IF output.

Claims

1. A mixer circuit, comprising:

a first transistor having a gate, a drain and a source, said source being coupled for receiving an RF signal, said gate being coupled to a first power supply conductor;

a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistors said gate being further coupled for receiving an LO signal, said source being coupled to said first power supply conductor, said drain providing an IF output signal; and

circuit means coupled between said source of said second transistor and said drain of said first transistor for providing a DC signal path between said source of said second transistor and said drain of said first transistor to allow said first and second transistors to share operating current.

2. The mixer circuit of claim 1 wherein said circuit means includes a first inductor coupled between said source of said second transistor and said drain of said first transistor.

3. The mixer circuit of claim 2 further including a first capacitor coupled between said source of said second transistor and said first power supply conductor.

4. The mixer circuit of claim 3 further including:

a first resistor coupled between an enable input and said gate of said second transistor; and

a second resistor coupled between said gate of said second transistor and said first power supply conductor.

5. The mixer circuit of claim 4 further including a second capacitor coupled between said drain of said second transistor and said source of said second transistor.

6. The mixer circuit of claim 5 further including a third resistor coupled between said source of said first transistor and said gate of said first transistor.

7. The mixer circuit of claim 6 further including:

a third capacitor;

a second inductor serially coupled with said third capacitor between said LO signal and said gate of said second transistor; and

a fourth capacitor coupled between said gate of said second transistor and said first power supply conductor.

8. The mixer circuit of claim 7 further including:

a third inductor coupled between a second power supply conductor and said drain of said second transistor; and

a fifth capacitor coupled between said first power supply conductor and said second power supply conductor.

9. The mixer circuit of claim 8 further including a sixth capacitor coupled between said drain of said first transistor and said gate of said second transistor.

10. A method of mixing an RF signal with an LO signal, comprising the steps of:

buffering the RF signal through a first transistor for providing a buffered RF signal;

mixing said buffered RF signal with the LO signal in a second transistor for providing an IF output signal; and

providing a DC signal path between a conduction path of said first transistor and a conduction path of said second transistor to allow said first and second transistors to share operating current.

11. The method of claim 10 further comprising the step of blocking said buffered RF signal and the LO signal through said DC signal path.

12. A mixer circuit, comprising:

a first transistor having a gate, a drain and a source, said source being coupled for receiving an RF signal, said gate being coupled to a first power supply conductor;

a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said gate being further coupled for receiving an LO signal, said source being coupled to said first power supply conductor, said drain providing an IF output signal; and

a first inductor coupled between said source of said second transistor and said drain of said first transistor for providing a DC signal path between said source of said second transistor and said drain of said first transistor to allow said first and second transistors to share operating current.

13. The mixer circuit of claim 12 further including a first capacitor coupled between said source of said second transistor and said first power supply conductor.

14. The mixer circuit of claim 13 further including:

a first resistor coupled between an enable input and said gate of said second transistor; and

a second resistor coupled between said gate of said second transistor and said source of said second transistor.

15. The mixer circuit of claim 14 further including a second capacitor coupled between said drain of said second transistor and said source of said second transistor.

16. The mixer circuit of claim 15 further including a third resistor coupled between said source of said first transistor and said first power supply conductor.

17. The mixer circuit of claim 16 further including:

a third transistor having a gate, a drain and a source, said gate being coupled to said first power supply conductor, said drain being coupled to said drain of said first transistor;

a third capacitor coupled between said LO signal and said source of said third transistor; and

a fourth resistor coupled between said source of said third transistor and said gate of said third transistor.

18. The mixer circuit of claim 17 further including:

a second inductor coupled between a second power supply conductor and said drain of said second transistor; and

a fourth capacitor coupled between said first power supply conductor and said second power supply conductor.

19. The mixer circuit of claim 18 further including a fifth capacitor coupled between said drain of said first transistor and said gate of said second transistor.