Method for designing low profile variable width input/output cells

• US 5,552,333 A
• Filed: 09/16/1994
• Issued: 09/03/1996
• Est. Priority Date: 09/16/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Nguyen, Trung, Atkinson, Kevin, Lozano, Elias, Colwell, Michael J., Cheung, Gary H.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/307,942
• Time in Patent Office: 718 Days
• Field of Search: 437/51, 257/786, 257/203, 364/491
• US Class Current: 438/129
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures

Abstract

An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

Claims

1. A method for maximizing the overall gate density in an integrated circuit chip comprising:

defining input/output band areas along the periphery of said integrated circuit chip said periphery comprising a plurality of peripheral edges,

dividing said input/output band areas into rectangular grid units having a width parallel to adjacent peripheral edge and a height perpendicular to said adjacent peripheral edge, each of said grid units having essentially the same width,

defining a plurality of input/output cells comprising one or more grid units, said cells having the same height as said grid unit height, and each of said plurality of input/output cells have a cell width essentially equal to the sum of the widths of said one or more of grid units depending on the different requirements of an input/output circuit to be contained therein, and

placing a plurality of bonding pads of essentially the same size along the input/output bands that are connected one each to the respective input/output cells.

2. The method as set forth in claim 1 where each of said bonding pads is associated with a particular input/output cell and each is placed next to and connected to said input/output cell such that there are no unconnected bonding pads associated with said input/output cell.

3. The method as set forth in claim 1 where the height of said input/output cells varies according to the usage of a last grid unit of said cell.

4. The method as set forth in claim 2 where the height of said input/output cells varies according to the usage of a last grid unit of said cell.

5. The method as set forth in claim 1 where said bonding pads are placed along an adjacent peripheral edge of the input/output band area.

6. The method as set forth in claim 5 where each of said bonding pads is associated with a particular input/output cell and each is placed next to and is connected to said input/output cell.

7. The method as set forth in claim 5 where the height of said input/output cells varies according to the usage of a last grid unit of said cell.

8. The method as set forth in claim 6 where the height of said input/output cells varies according to the usage of a last grid unit of said cell.

9. A method for increasing gate capacity in an integrated circuit chip comprising the steps of:

defining input/output band areas along a periphery of said integrated circuit chip, said periphery comprising a plurality of peripheral edges;

dividing said input/output band areas into rectangular grid units having a width parallel to a adjacent peripheral edge and a height perpendicular to said adjacent peripheral edge, each of said grid units having a constant width unit;

defining a plurality of input/output cells comprising one or more grid units, said cells having the same height as said grid unit height, and each of said plurality of input/output cells has a cell width related to the number of grid units depending on the different requirements of an input/output circuit to be contained therein, and said height being reduced in proportion to the amount that one or more grid units are unused;

placing a plurality of bonding pads along the input/output band that are connected to the respective input/output cells; and

creating a gate area within said band areas that is increased due to the decreased in height of said cells.

10. The method for increasing gate capacity of claim 9, wherein of said bonding pads are associated with at least one of said input/output cells.