Transistor-level timing and simulator and power analyzer

• US 5,553,008 A
• Filed: 07/10/1995
• Issued: 09/03/1996
• Est. Priority Date: 03/29/1993
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: EPIC Design Technology, Inc. (Synopsys Incorporated)
• Inventors: Huang, Xiaoli, Zhang, William H.
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/500,304
• Time in Patent Office: 421 Days
• Field of Search: 364/578, 364/488, 364/489, 364/490, 364/483, 364/DIG. 1, 364/232.3, 371/26, 371/27, 395/916
• US Class Current: 703/14
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method for accurately simulating the timing and power behavior of digital MOS circuits is provided. The method includes piece-wise linear modeling of transistors, dynamic and static construction of channel connected components, event driven simulation and current measuring capabilities for power supplies, grounds, and individual resistors and transistors.

Claims

1. In an appropriately programmed digital computer having a CPU, memory, user interface and printer, a method of simulating electronic circuits and analyzing these circuits with respect to timing behavior and power consumption comprising the steps of:

a) inputting a netlist of a circuit to be simulated identifying transistors and nodes;

b) inputting a technology file for characterizing transistors in said netlist, wherein said technology file initially contains a two-dimensional I-V table tabulating transistor drain to source currents at various drain-to-source and gate-to-source voltage pairs, said I-V table being subsequently converted into a two-dimensional linearization table holding piece-wise linear elements approximating MOS transistors;

c) inspecting each node in said netlist and constructing a static channel connected component at said each node where more than one transistor channel is coupled to said each node and where node quantity in said static channel connected component is below a maximum threshold value, said static channel connected component being stored in memory;

d) establishing initial voltage values at said each node in said netlist through input vectors;

e) advancing circuit simulation to a pending event next in time, wherein said pending event is a voltage change on a node that exceeds an event resolution, said voltage change being determined from a previous voltage level which caused an earlier event at said node;

f) identifying an affected transistor coupled to said node on which said pending event next in time is to occur;

g) associating an affected channel connected component with said affected transistor;

h) evaluating a response of said affected channel connected component to said pending event next in time through linear approximation, wherein each transistor contained in said affected channel connected component is replaced with a current source, resistor and transconductor retrieved from said technology file, said evaluating step including;

i) checking nodes contained in said affected channel connected component for event occurrence; and

ii) scheduling an event occurrence when detected.

2. The method as recited in claim 1, wherein the step of associating an affected channel connected component with said affected transistor is a step of retrieving from memory a static channel connected component containing said affected transistor.

3. The method as recited in claim 2, wherein the step of associating an affected channel connected component with said affected transistor further comprises the step of constructing a dynamic channel connected component containing said affected transistor when no static channel connected component is available.

4. The method as recited in claim 3, wherein the step of evaluating a response of said affected channel connected component to said pending event next in time further comprises the steps of:

a) solving in one iteration over a time delta a set of linear equations approximating said affected channel connected component for a node voltage level; and

b) reducing said time delta and re-solving said set of linear equations when said node voltage level exceeds a previous node voltage level by a predetermined error threshold.

5. The method as recited in claim 4, wherein the step of evaluating a response of said affected channel connected component to said pending event next in time further comprises the steps of:

a) recording changes in current and corresponding simulation time for a transistor connected to a power node and included in said affected channel connected component; and

b) outputting current and corresponding simulation time values for said power node based on said changes in current for said connected transistor.

6. The method as recited in claim 4, wherein the step of evaluating a response of said affected channel connected component to said pending event next in time further comprises the steps of:

a) recording changes in current and corresponding simulation time for a first transistor connected to a power node and included in said affected channel connected component;

b) recording changes in current and corresponding simulation time for a second transistor connected to said power node and included in said affected channel connected component;

c) outputting current and corresponding simulation time values for said power node based on said changes in current for said first and said second connected transistors.

7. The method as recited in claim 5, wherein the step of evaluating a response of said affected channel connected component to said pending event next in time further comprises the steps of:

a) recording changes in current and corresponding simulation time for a transistor specified by a user and included in said affected channel connected component; and

b) outputting current and corresponding simulation time values for said transistor specified by a user.

8. The method as recited in claim 5, wherein the step of evaluating a response of said affected channel connected component to said pending event next in time further comprises the steps of:

a) recording changes in current and corresponding simulation time for a resistor specified by a user and included in said affected channel connected component; and

b) outputting current and corresponding simulation time values for said resistor specified by a user.

9. The method of claim 1 wherein said gate to source voltage applied to said two-dimensional I-V table is an effective gate to source voltage, said effective gate to source voltage being a function of a threshold voltage of a MOS transistor.

10. The method of claim 9 wherein said technology file includes a linear approximation of a body bias voltage and threshold voltage relationship for a MOS transistor, said linear approximation being used to modify said threshold voltage value due to body bias effects, said modified threshold voltage used to determine said effective gate-to-source voltage.

11. The method of claim 5 further comprising the step of calculating average current provided by said power node, wherein a calculation is performed producing a partial value of average current at said power node after a change in current at said power node, said partial value being temporarily stored in memory.

12. The method of claim 5 further comprising the step of calculating root-mean-square current of said power node, wherein a calculation is performed producing a partial result after a change in current at said power node, said partial value being temporarily stored in memory.

13. In an appropriately programmed digital computer having a CPU, memory, user interface and printer, a method of simulating electronic circuits and analyzing these circuits with respect to timing behavior and power consumption comprising the steps of:

a) inputting a netlist of a circuit to be simulated identifying transistors and nodes;

b) inputting a technology file for characterizing transistors in said netlist, wherein said technology file initially contains a two-dimensional I-V table tabulating transistor drain to source currents at various drain-to-source and gate-to-source voltage pairs, said I-V table being subsequently converted into a two-dimensional linearization table holding piece-wise linear elements approximating MOS transistors;

c) inspecting each node in said netlist and constructing a static channel connected component at said each node where more than one transistor channel is connected to said each node and where node quantity in said static channel connected component is below a maximum threshold value, said static channel connected component being stored in memory;

d) establishing initial voltage values at said each node in said netlist through input vectors;

e) advancing circuit simulation to a first and a second pending event, wherein each pending event is a voltage change on a node that exceeds an event resolution, said voltage change being determined from a previous voltage level which caused an earlier event at said node;

f) identifying a first affected transistor coupled to a node on which said first pending event is to occur;

g) identifying a second affected transistor coupled to a node on which said second pending event is to occur;

h) associating a first and a second affected channel connected component with said first and second affected transistors, respectively;

i) evaluating a response of said first affected channel connected component to said first pending event through linear approximation, wherein each transistor contained in said first channel connected component is replaced with a current source, resistor and transconductor retrieved from said technology file, said evaluating step of said first affected channel connected component including;

i) checking nodes contained in said first channel connected component for event occurrence;

ii) scheduling an event occurrence when detected; and

iii) recording changes in current and corresponding simulation time for a first transistor connected to a power node and included in said first affected channel connected component;

j) evaluating a response of said second affected channel connected component to said second pending event through linear approximation, wherein each transistor contained in said second channel connected component is replaced with a current source, resistor and transconductor retrieved from said technology file, said evaluating step including;

i) checking nodes contained in said second channel connected component for event occurrence;

ii) scheduling an event occurrence when detected; and

iii) recording changes in current and corresponding simulation time for a second transistor connected to said power node and included in said second affected channel connected component;

k) Outputting current and corresponding simulation time values for said power node based on said changes in current of said first and said second connected transistors.

14. The method as recited in claim 13, wherein the step of associating a first and a second affected channel connected component with said first and second affected transistors is a step of retrieving from memory a first static channel connected component containing said first affected transistor.

15. The method as recited in claim 14, wherein the step of associating a first and a second affected channel connected component with said first and second affected transistors further comprises the step of constructing a first dynamic channel connected component containing said first affected transistor when no first static channel connected component is available.

16. The method as recited in claim 15, wherein the step of evaluating a response of said first affected channel connected component to said first pending event further comprises the steps of:

a) solving in one iteration over a time delta a set of linear equations approximating said first affected channel connected component for a node voltage level; and

b) reducing said time delta and re-solving said set of linear equations when said node voltage level exceeds a previous node voltage level by a predetermined error threshold.

17. The method as recited in claim 15, wherein the step of evaluating a response of said first affected channel connected component to said first pending event further comprises the steps of:

a) creating a set of linear equations approximating said first affected channel connected component, wherein said set of linear equations satisfies a constraint that a summation of all currents toward a node is zero;

b) solving in one iteration over a time delta said set of linear equations for a node voltage level; and

c) reducing said time delta and re-solving said set of linear equations when said node voltage level exceeds a previous node voltage level by a predetermined error threshold.

18. The method as recited in claim 15, wherein the step of evaluating a response of said first affected channel connected component to said first pending event further comprises the steps of:

a) creating a set of linear equations approximating said first affected channel connected component, wherein said set of linear equations satisfies a constraint that a summation of all voltage drops around a loop is zero;

b) solving in one iteration over a time delta said set of linear equations for a node voltage level; and

c) reducing said time delta and re-solving said set of linear equations when said node voltage level exceeds a previous node voltage level by a predetermined error threshold.

19. The method as recited in claim 16, wherein the step of evaluating a response of said first affected channel connected component to said first pending event further comprises the steps of:

a) recording changes in current and corresponding simulation time for a transistor specified by a user and included in said first affected channel connected component; and

b) outputting current and corresponding simulation time values for said transistor specified by a user.