Write-once read-many memory using EEPROM cells

• US 5,553,019 A
• Filed: 01/23/1995
• Issued: 09/03/1996
• Est. Priority Date: 01/23/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sandvos, Jerry L., Alton, Kenneth D.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/376,518
• Time in Patent Office: 589 Days
• Field of Search: 365/104, 365/900, 365/185, 365/195, 365/201, 365/185.04, 365/185.29
• US Class Current: 365/185.04
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A write-once read-many memory system (10) for electronically securing a select portion of memory from being overwritten or erased. Memory system (10) includes one or more storage cells (25) for providing electronic storage of information. A control cell (13) is used for controlling writing and/or erasing access to the storage cells (25). Control logic (11) is provided to control access to the control cell (13). Control cell (13) and control logic (11) are used as a gate to provide selective access to storage cells (25) through write control line (19) and erase control line (21). Storage cells (25) can only be accessed when the control cell (13) in an appropriate logic state.

Claims

1. A write-once read-many memory system comprising:

a first memory cell for providing electronic storage of information;

a second memory cell for controlling writing access to said first memory cell;

access means for providing access to said second memory cell;

a first bus connected to said first memory cell and said second memory cell for proving read logic information;

a second bus connected to said first memory cell and said second memory cell for providing write logic information;

a third bus connected to said first memory cell and said second memory cell for providing erase information;

wherein said access means comprises;

a first logic gate for controlling access to said second bus;

a second logic gate for controlling access to said third bus; and

a third logic gate for controlling access to said first logic gate and said second logic gate; and

wherein said second memory cell provides selective access to said first memory cell to allow said first memory cell to write or erase said information when said second memory cell is in an appropriate logic state and further wherein said third logic gate includes an input for receiving logic information from said second memory cell and a test node.

2. A write-once read-many memory system as in claim 1 wherein said test node is positioned within a chip carrier with said first memory cell and said second memory cell for providing limited access to said test node.

3. A write-once read-many memory system as in claim 1 wherein said first memory cell is an electrically erasable programmable read only memory.

4. A write-once read-many memory system as in claim 1 wherein said second memory cell is an electronically erasable programmable read only memory.

5. A write-once read-many memory system as in claim 1 wherein said access means includes at least one logic gate.

6. A write-once read-many memory system as in claim 1 wherein said first logic gate and said second logic gate are AND gates.

7. A write-once read-many memory system as in claim 6 wherein said third logic gate is a NAND gate.

8. A memory network which includes a device which enables information to be written into a memory cell one time and read from said memory cell any number of times, said memory network comprising:

at least one electronically erasable memory storage cell for storing logic information;

an electronically erasable memory control cell for controlling access to said at least one electronically erasable memory storage cell;

a read control bus for providing read data from said at least one electronically erasable storage cell and said electronically erasable memory control cell;

a write control bus for providing write data to said at least one electronically erasable memory storage cell and said electronically erasable memory control cell;

an erase control bus for providing erasing data to said at least one electronically erasable memory storage cell and said electronically erasable memory control cell;

a first gate for controlling operation of said write control bus;

a second gate for controlling operation of said erase control bus;

a third gate for controlling access to said electronically erasable memory storage cell and said electronically erasable memory control cell;

a control node connected to said third gate for providing logic information to access said third gate; and

wherein said at least one electronically erasable memory storage cell and said electronically erasable memory control cell are EEPROM and further wherein said first gate and said second gate are AND gates and said third gate is a NAND gate.

9. A memory network as in claim 8 wherein said control node is provided with said at least one electronically erasable memory storage cell and said electronically erasable memory control cell on an integrated circuit and said control node is inaccessible outside said integrated circuit for preventing unauthorized access to said at least one electronically erasable memory storage cell.