Structure and method for low current programming of flash EEPROMs

• US 5,553,020 A
• Filed: 08/31/1995
• Issued: 09/03/1996
• Est. Priority Date: 06/28/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Keeney, Stephen N., Atwood, Gregory E.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/521,656
• Time in Patent Office: 369 Days
• Field of Search: 365/185.19, 365/185.24, 365/185.28, 365/185.29, 365/185.30, 395/430, 395/164
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5622 Concurrent multilevel programming of more than one cell
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A system and method for programming non-volatile memory enables fast low current programming. Low current programming is achieved by applying a source bias voltage and increasing the drain voltage to be greater than the source bias voltage to maintain fast programming. Furthermore, the control gate voltage may be stepped or ramped from a minimum value to a maximum value to further reduce the peak channel current and to allow the flash cell threshold voltage to be placed to an exact value, for MLC applications. Ramping or stepping of the control gate may be done independently or in conjunction with an applied source bias voltage. Furthermore, the reduced cell current allows more cells to be programmed in parallel which improves program performance and the drain select device can be reduced in size to reduce die area.

Claims

1. A system comprising:

a processor; and

a memory coupled to the processor, said memory comprising;

a memory array comprising a plurality of cells, each cell comprising a floating gate, control gate, source junction and drain junction; and

programming circuitry for programming a cell by applying an initial gate voltage to the control gate of the cell, and stepping the control gate voltage in predetermined increments to a maximum gate voltage, applying a source bias voltage to the source junction of the cell, and applying a drain voltage pulse to the drain junction of the cell to cause hot electron injection of electrons onto the floating gate, said drain voltage pulse applied at each stepped increment of the control gate voltage;

said processor issuing control signals to the programming circuitry to program the cell.

2. The system as set forth in claim 1, wherein said programming circuitry further comprises at least one source bias resistor coupled to the source junction to provide the source bias voltage to the source junction.

3. The system as set forth in claim 1, wherein said programming circuitry further comprises a plurality of source bias resistors, one source bias resistor coupled to each source junction of each cell.

4. The system as set forth in claim 1, wherein said programming circuitry further comprises a plurality of source resistors, one source resistor coupled to a group of cells, wherein when a cell of a group is programmed, the source resistor provides the source bias voltage to the source junction.

5. The system as set forth in claim 1, wherein said programming circuitry programs a plurality of cells in parallel.

6. The system as set forth in claim 1, wherein said memory array further comprises at least one well, at least one cell located within the at least one well, said programming circuitry applying a negative well bias voltage to the well and applying approximately a zero source bias voltage to the source junction of the cell located within the well.

7. The system as set forth in claim 1, wherein the cell is a multilevel cell.

8. The system as set forth in claim 1, wherein the cell is a flash EEPROM cell.