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Structure and method for low current programming of flash EEPROMs

  • US 5,553,020 A
  • Filed: 08/31/1995
  • Issued: 09/03/1996
  • Est. Priority Date: 06/28/1994
  • Status: Expired due to Term
First Claim
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1. A system comprising:

  • a processor; and

    a memory coupled to the processor, said memory comprising;

    a memory array comprising a plurality of cells, each cell comprising a floating gate, control gate, source junction and drain junction; and

    programming circuitry for programming a cell by applying an initial gate voltage to the control gate of the cell, and stepping the control gate voltage in predetermined increments to a maximum gate voltage, applying a source bias voltage to the source junction of the cell, and applying a drain voltage pulse to the drain junction of the cell to cause hot electron injection of electrons onto the floating gate, said drain voltage pulse applied at each stepped increment of the control gate voltage;

    said processor issuing control signals to the programming circuitry to program the cell.

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