Packetized remote test system for a telephone network

• US 5,553,056 A
• Filed: 10/24/1994
• Issued: 09/03/1996
• Est. Priority Date: 04/02/1992
• Status: Expired due to Term

• Current Assignee: Viavi Solutions, Inc. (Lumentum Holdings Inc.)
• Original Assignee: Applied Digital Access, Inc. (Lumentum Holdings Inc.)
• Inventors: Hartmann, Paul R., Pope, Kevin T., Bronte, Jeffery S., Lever, Mark J.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US08/330,214
• Time in Patent Office: 680 Days
• Field of Search: 370/13, 370/14, 370/17, 370/85.1, 370/84, 370/92, 370/94.1, 370/94.2, 371/20.1, 379/1, 379/9, 379/10, 379/11, 379/12, 379/14, 379/15, 379/16
• US Class Current: 370/253
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04J 3/0623 Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04M 3/22 Arrangements for supervision, monitoring or testing
• CPC Class Codes: H04M 3/244 for multiplex systems

Abstract

A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. A second embodiment of the invention partitions the system into a base subsystem, a communications link and a remote subsystem, collectively referred to as a distributed architecture system. The distributed architecture system provides all of the performance monitoring and testing capabilities of the existing access system. The distributed architecture system provides a mechanism to transport a plurality of asynchronous and rate independent signals across the link to permit remote testing of digital and voice DS0 frequency circuits. In the preferred embodiment, the link that connects the base to the remote system is a standard DS1 channel. The clocks for the transmit and receive paths are derived from the same source, thus providing a common reference clock to both ends of the link. At the base site, the channels undergoing test are embedded DS0 channels within a DS3 signal accessed through a DS3 interface at the remote site.

Claims

1. A system for remotely accessing any one of a plurality of asynchronous signals embedded in a signal, comprising:

a communications channel connecting a base subsystem to a remote subsystem;

the remote subsystem, comprising;

an access circuit receiving and accessing the asynchronous signals embedded in the signal;

a remote bus transporting data representative of each accessed asynchronous signal;

a remote packet processor connected to the remote bus and the communications channel, wherein said remote packet processor packetizes the data received from the remote bus and transmits the packetized data to the base subsystem across the communications channel, and wherein said remote packet processor receives packetized data from the base subsystem across the communications channel and de-packetizes the packetized data for transmission to the remote bus;

the base subsystem, comprising;

a base bus transporting data representative of each accessed asynchronous signal;

a base packet processor connected to the base bus and the communications channel, wherein said base packet processor receives packetized data from the remote subsystem across the communications channel and de-packetizes the packetized data for transmission to the base bus, and wherein said base packet processor packetizes the data received from the base bus and transmits the packetized data to the remote subsystem across the communications channel;

a test resource that receives data from the base bus, wherein said test resource provides testing functions, and wherein said test resource transmits data to the base bus.

2. The system defined in claim 1, wherein a portion of the remote packet processor that receives data from the remote bus and transmits packetized data across the communications channel comprises:

a remote bus receiver receivably connected to the remote bus so as to receive data from the remote bus;

a remote packetizer receivably connected to the remote bus receiver, said remote packetizer receiving the remote bus data and assembling the remote bus data into one or more packets of a selected integer multiple of bytes, the packet having a control portion and a data portion; and

a remote transmitter receivably connected to the remote packetizer for transmitting the packets across the communications channel.

3. The system defined in claim 2, wherein the remote bus receiver comprises:

a control circuit connected to the remote bus;

a transmit buffer storing data received from the control circuit; and

a packetizer interface circuit for controlling transfer of the buffered data to the packetizer.

4. The system defined in claim 3, wherein the control circuit accesses data communicated in PCM format on the remote bus.

5. The system defined in claim 3, additionally comprising a configuration memory for configuring the accessed asynchronous signal in the remote bus, said configuration memory connected to the remote bus, the control circuit and the packetizer interface circuit.

6. The system defined in claim 2, additionally comprising a DS1 framer that identifies a valid DS1 frame synchronization bit of the packetized data on the communication channel between the base and remote subsystems, said framer connected between the remote packetizer and the remote transmitter.

7. The system defined in claim 2, wherein the control portion of the packet includes a frame relay header.

8. The system defined in claim 2, wherein the control portion of the packet includes a cyclic redundancy check field.

9. The system defined in claim 2, wherein the data portion of the packet is of a variable size.

10. The system defined in claim 2, wherein the packet is of one of the following types:

DS0 data packet and inter-processor communications (IPC) packet.

11. The system defined in claim 10, wherein the data portion of the DS0 packet comprises up to 267 bytes and the IPC packet comprises up to 500 bytes.

12. The system defined in claim 2, wherein said remote packetizer additionally assembles control packets.

13. The system defined in claim 1, wherein the signal comprises DS3 data and each of the asynchronous embedded signals comprises DS0 data.

14. The system defined in claim 1, wherein a portion of the base packet processor that receives packetized data from across the communication channel and transmits de-packetized data to the base bus comprises:

a base receiver receivably connected to the communications channel so as to receive data packets from the channel;

a base de-packetizer receivably connected to the base receiver, said base de-packetizer receiving the data packets and disassembling each received packet into a selected integer multiple of bytes, each packet having a control portion and a data portion; and

a base bus transmitter receivably connected to the base de-packetizer.

15. The system defined in claim 14, wherein the base bus transmitter comprises:

a de-packetizer interface circuit for controlling transfer of the data from the de-packetizer;

a receive buffer storing data received from the de-packetizer; and

a control circuit receivably connected to the receive buffer, said control circuit further connected to the base bus.

16. The system defined in claim 15, wherein the control circuit provides data on the base bus communicated in PCM format.

17. The system defined in claim 15, additionally comprising a configuration memory for configuring the accessed asynchronous signal in the base bus, said configuration memory connected to the base bus, the control circuit and the de-packetizer interface circuit.

18. The system defined in claim 1, wherein the test resource comprises:

a test resource receiver receivably connected to the base bus so as to provide base bus data to the test resource;

a processor for testing the data received from the base bus;

a test resource transmitter receivably connected to the processor so as to read test data from the processor and communicate the test data to the base bus.

19. The system defined in claim 1, wherein a portion of the base packet processor that receives data from the base bus and transmits packetized data across the communication channel comprises:

a base bus receiver receivably connected to the base bus so as to receive data from the base bus;

a base packetizer receivably connected to the base bus receiver, said remote packetizer receiving base bus data and assembling the data into a packet of a selected integer multiple of bytes, each packet having a control portion and a data portion; and

a base transmitter receivably connected to the base packetizer.

20. The system defined in claim 19, wherein the base bus receiver comprises:

a control circuit connected to the base bus;

a transmit buffer storing data received from the control circuit; and

a packetizer interface circuit for controlling transfer of the buffered data to the packetizer.

21. The system defined in claim 20, wherein the control circuit accesses data communicated in PCM format on the base bus.

22. The system defined in claim 20, additionally comprising a configuration memory for configuring the accessed asynchronous signal in the base bus, said configuration memory connected to the base bus, the control circuit and the packetizer interface circuit.

23. The system defined in claim 1, wherein a portion of the remote packet processor that receives packetized data from across the communication channel and transmits de-packetized data to the remote bus comprises:

a remote receiver receivably connected to the communications channel so as to receive data packets from the channel;

a remote de-packetizer receivably connected to the remote receiver, said remote de-packetizer receiving the received data packets and disassembling each received packet into a stream of data of a selected integer multiple of bytes, each packet having a control portion and a data portion; and

a remote bus transmitter receivably connected to the remote de-packetizer.

24. The system defined in claim 23, wherein the remote bus transmitter comprises:

a de-packetizer interface circuit for controlling transfer of the data from the de-packetizer;

a receive buffer storing data received from the de-packetizer; and

a control circuit receivably connected to the receive buffer, said control circuit further connected to the remote bus.

25. The system defined in claim 24, wherein the control circuit provides data on the remote bus communicated in PCM format.

26. The system defined in claim 24, additionally comprising a configuration memory for configuring the accessed asynchronous signal in the remote bus, said configuration memory connected to the remote bus, the control circuit and the de-packetizer interface circuit.

27. The system defined in claim 1, wherein the communications channel transports a DS1 signal.

28. The system defined in claim 1, wherein the remote bus transports asynchronous time slot data.

29. The system defined in claim 1, wherein the base bus transports asynchronous time slot data.

30. The system defined in claim 1, wherein the base subsystem and remote subsystem each additionally comprise a channel rate control element.

31. The system defined in claim 30, wherein the remote subsystem channel rate control element comprises feedback control means.

32. The system defined in claim 31, wherein the feedback control means generates a remote to base control packet.

33. The system defined in claim 32, wherein the remote to base control packet includes a packet rate control field.

34. The system defined in claim 33, wherein the feedback control means comprises a mechanism to determine the value of the packet rate control field.

35. The system defined in claim 32, wherein the remote to base control packet includes a rate control information field associated with one of the asynchronous signals.

36. The system defined in claim 30, wherein the base subsystem channel rate control element comprises a base receive portion for matching a data rate of the base bus to a data rate of the remote bus.

37. The system defined in claim 36, wherein the base receive portion controls the data rate of the base bus in response to the rate specified by the packet received from the communications channel.

38. The system defined in claim 30, wherein the base subsystem channel rate control element additionally comprises a base transmit portion that controls the rate of data transfer from the test resource to the base bus.

39. The system defined in claim 36, wherein the asynchronous signals comprise DS0 signals.

40. The system defined in claim 39, wherein the data rate of the remote bus is derived from a one of the DS0 signals.

41. The system defined in claim 30, wherein the base subsystem additionally comprises a base bus rate control subsystem.

42. The system defined in claim 41, wherein the base bus rate control subsystem comprises:

a base bus control circuit;

a configuration memory connected to the control circuit; and

a processor connected to the control circuit and to the configuration memory, wherein the processor modulates the data rate of the base bus for each accessed asynchronous signal by enabling and disabling an enable bit in the configuration memory.

43. The system defined in claim 42, wherein the processor receives a headroom value from the base channel rate control element, said headroom value controlling a data rate of the base bus.

44. In a system having a base location, a remote location and a communications link between the base and remote locations, a method for accessing a selected one of a plurality of asynchronous embedded channels in a signal received at the remote location, comprising the steps of:

accessing, at the remote location, the selected one of the asynchronous embedded channels;

placing a portion of the data in the selected channel on a remote bus;

transporting the data on the remote bus;

extracting the data on the bus;

packetizing the extracted data;

transmitting the packetized data over the communications link;

receiving the packetized data at the base location;

de-packetizing the received data; and

inserting the de-packetized data onto a base bus.

45. The method defined in claim 44, additionally comprising the steps of:

transmitting each packet of the packetized data a second time; and

selecting a non-errored packet between the two packets.

46. The method defined in claim 44, additionally comprising the step of testing the data on the base bus.

47. The method defined in claim 46, wherein the testing step includes replacing selected data with test data.

48. The method defined in claim 47, additionally comprising the steps of:

inserting, at the base location, test data onto the base bus;

transporting the test data on the base bus;

extracting the test data from the base bus;

packetizing the extracted data;

transmitting the packetized data over the communications link;

receiving the packetized data at the remote location;

de-packetizing the received data;

inserting the de-packetized data onto the remote bus;

transporting the data on the remote bus;

extracting the data from the remote bus; and

inserting the data into the embedded channel.

49. The method defined in claim 44, wherein data is placed into a selected time slot on the remote bus.

50. The method defined in claim 48, wherein data is placed into the selected time slot on the base bus.

51. In a system having a base location including a base bus, a remote location including a remote bus, and a communications link between the base and remote locations, a method for accessing a selected one of a plurality of asynchronous embedded channels in a signal received at the remote location, comprising the steps of:

accessing, at the remote location, the selected one of the asynchronous embedded channels;

transmitting packetized data over the communications link representative of the accessed channel;

testing the data on the base bus, thereby producing tested data;

transmitting the packetized data representative of the tested data over the communications link; and

inserting the data into the embedded channel.

52. A system for accessing a selected one of a plurality of asynchronous signals embedded in a signal received at a remote location, comprising:

remote means for remotely accessing the asynchronous signals embedded in the signal;

base means for testing the embedded asynchronous signals; and

a packet data link connecting the remote access means and the base test means, wherein data on said link comprises packets.

53. The system defined in claim 52, wherein each of the embedded asynchronous signals comprises a DS0 signal.