Fully digital data separator and frequency multiplier

• US 5,553,100 A
• Filed: 04/01/1994
• Issued: 09/03/1996
• Est. Priority Date: 04/01/1994
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Shacham, Alon, Saban, Rami, Efendovich, Avner, Karpati, Varda
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Shankar, Vijay
• Application Number:
  US08/221,618
• Time in Patent Office: 886 Days
• Field of Search: 375/94, 375/110, 375/118-120, 375/340, 375/359, 375/360, 375/371, 375/373, 375/375, 375/376, 327/156, 327/160, 327/166
• US Class Current: 375/340
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a "fast" clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted. The output of the data separator is generated by a decrementing register, the phase or frequency of the data separator being adjusted by increasing or decreasing the initial value loaded into the decrementing register. The data separator is fully digital.

Claims

1. A digital data separator for receiving a data input signal over a serial data in (SDI) line and delivering a clock signal output, said digital data separator comprising:

an early and late logic unit, said early and late logic unit comprising;

a phase shift accumulator (PSA) register having an input, said PSA register being actuated via said input so as to change a binary value stored in said PSA register when a phase difference exists between said data input signal and said clock signal output, and

a limit detector connected to said PSA register, said limit detector delivering an output when the binary value stored in said PSA register reaches a predetermined limit;

a bit length register (BLR) logic unit, said BLR logic unit comprising a counter register, said counter register counting at a fast clock rate, said output from said limit detector controlling the magnitude of a binary value to be loaded into said counter register; and

a counter oscillator, said counter oscillator receiving a signal from said BLR logic unit when said counter register reaches a selected binary value, said counter oscillator delivering said clock signal output in response to said signal from said BLR logic unit.

2. The digital data separator of claim 1, said BLR logic unit further comprising a temporary bit length register (TBLR), a binary value stored in said TBLR capable of being adjusted in response to said output from said limit detector, said binary value stored in said TBLR being loaded into said counter register and thereby controlling the phase of said clock signal output.

3. The digital data separator of claim 2, said BLR logic unit further comprising a bit length register (BLR), a binary value stored in said BLR capable of being adjusted in response to said output from said limit detector, a selected portion of said binary value stored in said BLR being loaded into said counter register and thereby controlling the frequency of said clock signal output.

4. The digital data separator of claim 1 wherein said PSA register counts in a first direction when said data input signal is late with respect to said clock signal output and counts in a second direction when said data input signal is early with respect to said clock signal output.

5. The digital data separator of claim 1 wherein said PSA register is incremented when said data input signal is late with respect to said clock signal output and is decremented when said data input signal is early with respect to said clock signal output.

6. The digital data separator of claim 5 wherein said early and late logic unit further comprises a temporary phase shift accumulator (TPSA) register, a binary value stored in said PSA register being loaded into said TPSA register at a midpoint of a data window of said data input signal and then reloaded into said PSA register at an end of said data window of said data input signal if no pulse is present in said data window.

7. The digital data separator of claim 2 further comprising a frequency and phase correction logic unit, said frequency and phase correction logic unit comprising a state machine, said state machine being connected to said output of said limit detector.

8. The digital data separator of claim 7 wherein said state machine is in a tracking state when said binary value stored in said PSA register is between an upper limit and a lower limit detected by said limit detector.

9. The digital data separator of claim 8 wherein said state machine moves from said tracking state to an increment TBLR state when said limit detector detects said upper limit, the arrival of said state machine at said increment TBLR state causing said TBLR to be incremented.

10. The digital data separator of claim 8 wherein said state machine moves from said tracking state to a decrement TBLR state when said limit detector detects said lower limit, the arrival of said state machine at said decrement TBLR state causing said TBLR to be decremented.

11. The digital data separator of claim 3 further comprising a frequency and phase correction logic unit, said frequency and phase correction logic unit comprising a state machine, said state machine being connected to said output of said limit detector.

12. The digital data separator of claim 11 wherein said state machine is in a tracking state when said binary value stored in said PSA register is between an upper limit and a lower limit detected by said limit detector.

13. The digital data separator of claim 12 wherein said state machine moves from said tracking state to an increment TBLR state when said limit detector detects said upper limit, the arrival of said state machine at said increment TBLR state causing said TBLR to be incremented.

14. The digital data separator of claim 13 wherein said state machine moves from said tracking state to an increment BLR state when said limit detector detects said upper limit a second time without having detected said lower limit, the arrival of said state machine at said increment BLR state causing said BLR to be incremented.

15. The digital data separator of claim 14 wherein said arrival of said state machine at said increment BLR state also causes said TBLR to be incremented.

16. The digital data separator of claim 13 wherein said state machine automatically moves to a pending state after said state machine arrives at said increment TBLR state.

17. The digital data separator of claim 14 wherein said state machine automatically moves to said tracking state after said state machine arrives at said increment BLR state.

18. The digital data separator of claim 1 further comprising a data detector connected to said counter oscillator, said data detector delivering a data signal.

19. The digital data separator of claim 18 wherein said data signal is a non-return-to-zero data signal.

20. The digital data separator of claim 18 wherein said data detector delivers a non-return-to-zero clock signal.

21. A digital data separator for receiving serial input data originating in a recording medium and generating in response to said serial input data a digital output signal, said digital data separator comprising:

an early and late logic unit, said early and late logic unit comprising a first register which records a cumulative phase difference between said serial input data and said digital output signal and generates an output when said cumulative phase difference reaches a predetermined level;

a bit length logic unit, said bit length logic unit comprising a second register, said second register cycling between a first binary value and a second binary value, said first binary value being variable, said output from said early and late logic unit controlling the magnitude of said first binary value thereby to control the time required for said second register to count from said first binary value to said second binary value; and

a counter oscillator, said counter oscillator receiving a bit detect signal when said second register reaches a predetermined binary value and responsively providing said digital output signal.

22. The digital data separator of claim 21 further comprising a means for changing the magnitude of said first binary value for a single cycle of said second register so as to alter the phase of said digital output signal.

23. The digital data separator of claim 22 further comprising a means for changing the magnitude of said first binary value during a plurality of cycles of said second register so as to alter the frequency of said digital output signal.

24. The digital data separator of claim 21 further comprising a means for changing the magnitude of said first binary value during a plurality of successive cycles of said second register so as to alter the frequency of said digital output signal.

25. The digital data separator of claim 21 wherein said bit length logic unit alters the phase of said digital output signal in response to an initial generation of said output of said early and late logic unit and alters the frequency of said digital output signal in response to a later generation of said output of said early and late logic unit.

26. The digital data separator of claim 21 wherein said first register is clocked at a fast clock rate which is greater than a clock rate of said serial input data, said first register counting in a first direction when a pulse of said serial input data arrives at said early and late logic unit before a selected point in a bit cell of said digital output signal, and counting in a second direction when said pulse of said serial input data arrives at said early and late logic unit after said selected point in said bit cell of said digital output signal.

27. The digital data separator of claim 26 wherein said first register begins counting in said first direction upon the arrival of said pulse before said selected point in said bit cell and stops counting upon the occurrence of said selected point in said bit cell.

28. The digital data separator of claim 27 wherein, if said pulse does not arrive before the occurrence of said selected point in said bit cell, said first register begins counting in said second direction upon the occurrence of said selected point in said bit cell and stops counting upon the arrival of said pulse after the occurrence of said selected point in said bit cell.

29. The digital data separator of claim 28 wherein said early and late logic unit contains a means for storing a binary value held in said first register and reloading said stored binary value into said first register in the event that no pulse of said serial input data arrives at said early and late logic unit during a given bit cell of said digital output signal.

30. A method of converting a serial data input to a digital output signal, said method comprising the steps of:

(a) digitally recording a cumulative phase difference between said serial data input and said digital output signal, said step (a) comprising.;

providing a first register;

causing said first register to count at a fast clock rate in a first direction when a pulse of said serial data input occurs before a selected point in a bit cell of said digital output signal; and

causing said first register to count at said fast clock rate in a second direction when a pulse of said serial data input occurs after said selected point in said bit cell of said digital output signal;

(b) detecting when said cumulative phase difference reaches a predetermined limit; and

(c) altering the phase and/or frequency of said digital output signal when said cumulative phase difference reaches said predetermined limit.

31. The method of claim 30 wherein step (a) further comprises:

when said pulse of said serial input data arrives before said selected point in said bit cell of said digital output signal, causing said first register to begin counting in said first direction upon the arrival of said pulse and causing said first register to stop counting upon the occurrence of said selected point in said bit cell of said digital output signal; and

when said pulse of said serial input data arrives after said selected point in said bit cell of said digital output signal, causing said first register to begin counting in said second direction upon the occurrence of said selected point in said bit cell of said digital output signal and causing said first register to stop counting upon the arrival of said pulse.

32. The method of claim 31 wherein step (a) further comprises storing a binary value held in said first register and reloading said value into said first register in the event that there is no pulse of said serial input data during a given bit cell of said digital output signal.

33. The method of claim 30 wherein said serial input data are encoded in the modified frequency modulation format.

34. The method of claim 30 wherein step (c) comprises:

providing a first register;

causing said first register to cycle repeatedly between a first binary value and a second binary value, said first binary value being variable; and

varying said first binary value so as to alter the time duration of a cycle of said first register.

35. The method of claim 34 wherein step (c) further comprises changing said first binary value from a first magnitude to a second magnitude for one cycle of said first register and then restoring said first binary value to said first magnitude, thereby altering the phase of said digital output signal.

36. The method of claim 34 wherein step (c) further comprises changing said first binary value for a succession of cycles of said first register, thereby altering the frequency of said digital output signal.

37. The method of claim 34 wherein step (c) further comprises:

providing second and third registers;

coupling said second register to said first register;

coupling said third register to said second register; and

before the beginning of each cycle of said first register, loading data said third register into said second register and then loading data from said second register into said first register, the data being loaded into said first register determining the duration of the next cycle of said first register.

38. The method of claim 37 further comprising the step of altering the data in said second register, said step of altering occurring after a transfer of data from said third register to said second register but before a transfer of data from said second register to said first register, the phase of said digital output signal thereby being shifted.

39. The method of claim 37 further comprising the step of altering the data in said third register, the frequency of said digital output signal thereby being changed.

40. The method of claim 39 wherein said second register has N bit locations and said third register has M bit locations, wherein N is less than M, and wherein the N most significant bit locations of said third register are connected to said second register.

41. The method of claim 40 further comprising the step of altering the data in said third register by an amount greater than or equal to 2.sup.(M-N), thereby altering the data transferred from said third register to said second register before a succession of cycles of said first register and changing the frequency of said digital output signal.

42. The method of claim 40 further comprising the step of causing the data held in said second register to be changed after each transfer of data from said third register to said second register but before the next transfer of data from said second register to said first register and thereby changing the frequency of said digital output signal.