Row addressable graphics memory with flash fill

• US 5,553,229 A
• Filed: 03/06/1995
• Issued: 09/03/1996
• Est. Priority Date: 11/15/1993
• Status: Expired due to Term

• Current Assignee: Animedia Company LLC (Intellectual Ventures LLC)
• Original Assignee: Jed Margolin
• Inventors: Margolin, Jed
• Primary Examiner(s): TUNG, KEE M
• Application Number:
  US08/398,994
• Time in Patent Office: 547 Days
• Field of Search: 395/162-166, 395/410, 395/411, 345/185, 345/196, 345/189, 345/200, 345/190, 365/189.01, 365/189.04, 365/189.05, 365/230.01, 365/230.03, 365/230.05, 365/230.08, 365/230.09, 365/230.12, 365/219
• US Class Current: 345/564
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A single-chip semiconductor memory device optimized for high performance flat-shaded polygon video systems consists of a RAM with flash fill circuitry whereby the Start and End addresses are specified for a given row; the data within this range are read, modified, and written back to the memory in parallel thereby requiring a maximum of three memory cycles to fill a line segment independent of the length of the line. The data are modified according to a function between a color register and the data already present in the memory array, the functions being: AND, OR, EXCLUSIVE OR, or REPLACE.

Claims

1. An apparatus for addressing and modifying display information for display on a display screen, said apparatus comprising:

(a) a row addressable memory for storing a plurality of lines of image data, said row addressable memory for receiving a row address, range data, and manipulation data, said range data defining a portion of image data at said row address to be modified according to said manipulation data;

(b) row address circuitry for selecting a particular row in said row addressable memory; and

(c) a plurality of circuit stages for accessing said row of image data, each circuit stage comprising a compare unit and a bit processing unit for each bit plane of said row addressable memory, said compare unit comprising;

(i) a first range circuit for comparing a first data of said range data with a fixed address corresponding to said circuit stage;

(ii) a second range circuit for comparing a second data of said range data with said fixed address; and

(iii) a first logic circuit responsive to outputs of said first range circuit and said second range circuit for determining if said fixed address of said circuit stage is within said range data; and

(d) said bit processing unit comprising a second logic circuit, responsive to said first logic circuit, for modifying data from said row of image data according to said manipulation data provided said fixed address of said circuit stage is within said range data.

2. An apparatus as described in claim 1 wherein said manipulation data comprises color data and logic function data and further comprising a memory device for storing said row of image data of said particular row for access by said plurality of circuit stages, said memory device coupled to said plurality of circuit stages.

3. An apparatus as described in claim 2 wherein said address range, as a maximum size, corresponds to a row of said row addressable memory corresponding to a line of said display screen.

4. An apparatus as described in claim 2 wherein said plurality of circuit stages comprise a fill unit.

5. An apparatus as described in claim 2 wherein said first range circuit is a comparator and wherein said second range circuit is a comparator.

6. An apparatus according to claim 5 wherein each input gate of said first range circuit for an input bit of said fixed address having a logic low value comprises an AND gate whose inputs comprise a corresponding bit from said first data of said range data and an output of a previous comparator gate of lesser weight, and wherein each input gate for said input bit of said fixed address having a logic high value comprises an OR gate whose inputs comprise said corresponding bit from said first data of said range data and said output of said previous comparator gate of lesser weight.

7. An apparatus according to claim 6 wherein each input gate of said second range circuit for an input bit of said fixed address having a logic low value comprises an AND gate whose inputs comprise a corresponding bit from said second data of said range data and an output of a previous comparator gate of lesser weight, and wherein each input gate for said input bit of said fixed address having a logic high value comprises an OR gate whose inputs comprise said corresponding bit from said second data of said range data and said output of said previous comparator gate of lesser weight.

8. An apparatus for addressing and modifying display information for display on a screen, said apparatus comprising:

(a) a row addressable memory for storing a plurality of lines of information, said row addressable memory for receiving a row address, color data, range data, and logic function data, said range data defining a portion of data at said row address to be modified according to said color data and said logic function data;

(b) row address circuitry for selecting a particular row in said row addressable memory for access of a row of data of said particular row;

(c) a data memory for storing said row of data of said particular row;

(d) a plurality of circuit stages for accessing said row of data, each circuit stage comprising a range compare unit and a bit processing unit for each bit plane of said row addressable memory, said range compare unit comprising;

(i) a first range circuit for comparing a first data of said range data with a fixed address corresponding to said circuit stage;

(ii) a second range circuit for comparing a second data of said range data with said fixed address; and

(iii) a first logic circuit for combining outputs of said first range circuit and said second range circuit for determining if said fixed address of said circuit stage is within said range data;

(e) said bit processing unit comprising a second logic circuit, responsive to said first logic circuit, for modifying data from said data memory according to said logic function data and said color data provided said fixed address of said circuit stage is within said range data.

9. An apparatus as described in claim 8 wherein said address range, as a maximum size, corresponds to a row of said row addressable memory corresponding to a line of said screen.

10. An apparatus as described in claim 8 wherein said plurality of circuit stages comprise a fill unit.

11. An apparatus as described in claim 8 wherein said first range circuit is a comparator and wherein said second range circuit is a comparator.

12. An apparatus according to claim 11 wherein each input gate of said first range circuit for an input bit of said fixed address having a logic low value comprises an AND gate whose inputs comprise a corresponding bit from said first data of said range data and an output of a previous comparator gate of lesser weight, and wherein each input gate for said input bit of said fixed address having a logic high value comprises an OR gate whose inputs comprise said corresponding bit from said first data of said range data and said output of said previous comparator gate of lesser weight.

13. An apparatus according to claim 12 wherein each input gate of said second range circuit for an input bit of said fixed address having a logic low value comprises an AND gate whose inputs comprise a corresponding bit from said second data of said range data and an output of a previous comparator gate of lesser weight, and wherein each input gate for said input bit of said fixed address having a logic high value comprises an OR gate whose inputs comprise said corresponding bit from said second data of said range data and said output of said previous comparator gate of lesser weight.

14. In a device comprising a display screen and a display screen controller, a method of addressing and modifying display information for display on said display screen, said method comprising the steps of:

(a) storing a plurality of lines of information into a row addressable memory;

(b) transferring to said row addressable memory a row address, color data, range data, and logic function data, wherein said range data defines a portion of data at said row address to be modified according to said color data and said logic function data;

(c) selecting a row of data corresponding to a particular row in said row addressable memory using row address circuitry;

(d) accessing said row of data by a plurality of circuit stages, each circuit stage comprising a range compare unit and a bit processing unit for each bit plane of said row addressable memory, said range compare unit performing the steps of;

(i) comparing a first address designator of said range data with a fixed address corresponding to said circuit stage using a first range circuit;

(ii) comparing a second address designator of said range data with said fixed address using a second range circuit; and

(iii) responsive outputs of said first range circuit and said second range circuit, determining if said fixed address of said circuit stage is within said range data;

(e) modifying data from said row of data according to said logic function data and said color data provided said fixed address of said circuit stage is within said range data, said step (e) of modifying responsive to said step of determining and performed by a second logic circuit of said bit processing unit.

15. A method of addressing and modifying display information as described in claim 14 wherein said address range, as a maximum size, corresponds to a row of said row addressable memory corresponding to a line of said screen.

16. A method of addressing and modifying display information as described in claim 14 wherein said plurality of circuit stages comprise a fill unit.

17. A method of addressing and modifying display information as described in claim 14 wherein said first range circuit is a comparator and wherein said second range circuit is a comparator.

18. A method of addressing and modifying display information as described in claim 17 wherein said step of comparing a first address designator of said range data with a fixed address comprises the steps of:

for an input bit of said fixed address having a logic low value, feeding a corresponding bit from said first address designator of said range data and an output of a previous comparator gate of lesser weight to an AND gate;

for said input bit of said fixed address having a logic high value, feeding a corresponding bit from said first address designator of said range data and said output of said previous comparator gate of lesser weight to an OR gate.

19. An method of addressing and modifying display information as described in claim 18 wherein said step of comparing a second address designator of said range data with a fixed address comprises the steps of:

for an input bit of said fixed address having a logic low value, feeding a corresponding bit from said second address designator of said range data and an output of a previous comparator gate of lesser weight to an AND gate; and

for said input bit of said fixed address having a logic high value, feeding a corresponding bit from said second address designator of said range data and said output of said previous comparator gate of lesser weight to an OR gate.