Vertex minimization in a smart optical proximity correction system

• US 5,553,274 A
• Filed: 06/06/1995
• Issued: 09/03/1996
• Est. Priority Date: 04/17/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Liebmann, Lars W.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US08/470,728
• Time in Patent Office: 455 Days
• Field of Search: 395/500, 395/921, 395/919, 395/920, 364/488, 364/489, 364/490, 364/491, 364/478, 250/492.2, 250/492.22, 430/5, 430/297, 430/314
• US Class Current: 716/53
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]

Abstract

An optical proximity correction (OPC) routine that enhances the fidelity of VLSI pattern transfer operations such as photolithography and reactive ion etch (RIE) by predistorting the mask while biasing only critical features and eliminating, as much as possible, the creation of additional vertices. The OPC routine accomplishes corrections in a timely and cost effective manner on realistic data sets without causing unnecessary increase in data volume. The OPC method employs a series of shrink, expand and subtraction operations that separate complex computer aided design (CAD) data for a lithography mask or reticle into sets of basic rectangles. More particularly, the OPC method first identifies a plurality of gate regions in a CAD design. A plurality of design shapes in the CAD design are sorted according to geometric type. A plurality of sorted design shapes share at least one side with a second design shape. The sorted design shapes are then grouped according to width. Finally, all of the grouped design shapes having been identified as gate regions are biased based on applicable OPC rules

Claims

1. A system for applying an optical proximity correction to chip designs to control accuracy in VLSI patterning operations, said system comprising:

graphics design means for generating an original design data set of a chip design;

shapes processor means for subjecting a level of the original design data set to a fracturing procedure including a series of shrink, expand and subtraction operations to fracture the design data set into a plurality of basic geometric shades abutting at vertices existent in the original design data set and sort the plurality of basic geometric shapes by width, said processor means locating and identifying relevant fractions of the sorted plurality of basic geometric shapes which are critical regions to the original design data set; and

postprocessor means for applying optical proximity correction biasing all of tractions having been identified as critical regions to the design data set.

2. The system for applying an optical proximity correction to chip designs to control the accuracy in patterning operations recited in claims 1 wherein said shapes processor means is programmed to iteratively shrink a first pattern by a predetermined amount equal to a minimum feature size in the level of the design, expand the pattern resulting from shrinking said first pattern by the predetermined amount to obtain a second pattern, subtract the second pattern from the first pattern to obtain a difference pattern, and repeat the shrink, expand and subtract operations until a maximum feature size has been reached, thereby generating a plurality of difference patterns.

3. The system for applying an optical proximity correction to chip designs to control the accuracy in VLSI patterning operations recited in claim 2 Wherein said shapes processor means is further programmed to combine the plurality of difference patterns to obtain a fractured design of the original design data set.