Method and apparatus for regulating the output voltage of negative charge pumps

• US 5,553,295 A
• Filed: 03/23/1994
• Issued: 09/03/1996
• Est. Priority Date: 03/23/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pantelakis, Dimitris, Tedrow, Kerry
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/217,094
• Time in Patent Office: 895 Days
• Field of Search: 395/750, 395/550, 363/59, 363/60, 365/226, 365/227, 365/229, 365/218, 327/530
• US Class Current: 713/300
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A regulation circuit which includes circuitry for furnishing a reference voltage, a voltage divider for furnishing a voltage provided by a charge pump circuit, a comparator for comparing the output of the charge pump circuit with the reference voltage, and apparatus for operating the charge pump when the voltage drops below the reference level and for interrupting operation of the charge pump when the voltage produced by the charge pump becomes greater than the reference voltage.

Claims

1. A regulation circuit, comprising:

a source of a reference voltage,

a charge pump circuit,

a first voltage divider circuit connected between an output of the charge pump and the source of reference voltage for furnishing a first voltage,

a second voltage divider connected between the source of reference voltage and a known voltage level for furnishing a second voltage,

a comparator for comparing the output of the charge pump circuit with the reference voltage, and

an oscillator for operating the charge pump when the first voltage is less than the second voltage and for interrupting operation of the charge pump when the first voltage is greater than the second voltage.

2. A regulation circuit as claimed in claim 1 in which each of the first and second voltage divider circuits includes a diode-connected transistor.

3. A regulation circuit as claimed in claim 2 in which the comparator is a differential amplifier circuit.

4. A regulation circuit as claimed in claim 1 in which the charge pump is a negative charge pump.

5. A regulation circuit as claimed in claim 1 in which the charge pump is a bootstrap charge pump, and the oscillator provides four trains of non-overlapping clock pulses for driving the charge pump.

6. A computer system, comprising:

a central processor;

a system bus coupled to the processor;

a main memory coupled to the system bus; and

a programmable non-volatile long term memory coupled to the system bus, further comprising

a flash EEPROM memory array, and

a circuit for furnishing voltages for operating the flash EEPROM memory array that further comprises

a source of a reference voltage,

a charge pump,

a first voltage divider circuit connected between an output of the charge pump and the source of reference voltage for furnishing a first voltage,

a second voltage divider connected between the source of reference voltage and a known voltage level for furnishing a second voltage,

a comparator for comparing the output of the charge pump circuit with the reference voltage, and

an oscillator for operating the charge pump when the first voltage is less than the second voltage and for interrupting operation of the charge pump when the first voltage is greater than the second voltage.

7. A computer system as claimed in claim 6 in which each of the first and second voltage divider circuits includes a diode-connected transistor.

8. A computer system as claimed in claim 6 in which the comparator is a differential amplifier circuit.

9. A computer system as claimed in claim 6 in which the charge pump is a negative charge pump.

10. A computer system as claimed in claim 6 in which the charge pump is a bootstrap charge pump, and

the oscillator provides four trains of non-overlapping clock pulses for driving the charge pump.