PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof

• US 5,554,552 A
• Filed: 04/03/1995
• Issued: 09/10/1996
• Est. Priority Date: 04/03/1995
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chi, Kao M.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/415,420
• Time in Patent Office: 526 Days
• Field of Search: 437/30, 437/43, 437/45, 437/46
• US Class Current: 438/264
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 438/901 Capacitive junction

Abstract

Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant instead of POCl₃ doping are required to fabricate this device. The threshold voltage of this device is well controlled by the ratio of C_fp, capacitance of the P type capacitor and C_fn capacitance of the N type capacitor. The coupling ratio "READ" and "WRITE" are exactly the same as current N type floating gate. The "ERASE" efficiency is improved by 1.5 volt higher voltage to the drain electrode of the EEPROM or the source electrode of a flash EPROM. Also, a good P-N junction floating gate, with reverse junction leakage less than 10 pA for 7 Volt reverse bias, is required to discharge the N type capacitor without affecting the P type capacitor.

Claims

1. A method of forming a floating gate ROM device comprising

providing a lightly doped P- semiconductor substrate,

forming a doped source region and a doped drain region in the substrate,

forming a tunnel oxide layer and field oxide regions formed over the surface of the substrate,

forming a PN junction floating gate electrode from a first polysilicon layer comprising doped polysilicon with an N doped region above the tunnel oxide layer and at least one P doped region above the field oxide region juxtaposed with the N doped region,

forming an intergate electrode dielectric layer covering the PN floating gate electrode,

forming a polysilicon control gate electrode from a second polysilicon layer over the intergate electrode dielectric layer, and

forming an additional dielectric layer over the control gate electrode.

2. A method in accordance with claim 1 wherein the PN junction is formed by the steps comprising

depositing a first polysilicon layer on the tunnel oxide layer and the field oxide regions,

performing a P-type capacitor implant into the first polysilicon layer,

forming a mask over the field oxide regions with openings over the tunnel oxide regions, and

performing a N-type capacitor implant into portions of the first polysilicon layer over the tunnel oxide regions through the openings in the mask.

3. A method in accordance with claim 1 wherein the PN junction is formed by the further steps comprising

performing a first polysilicon layer P-type capacitor implant is performed into the first polysilicon layer with a blank-maskless P type implant of P- boron ions into the first polysilicon layer with a dose from about 1×

10¹⁴ /cm² to about 3×

10¹⁴ /cm², and

formation of a first polysilicon layer N-type capacitor implant mask with openings therein is formed upon the device followed by an N-type capacitor implant into portions of the first polysilicon layer through openings in the mask with an ion implant of N type ions selected from the group consisting of arsenic and phosphorus ions to form N+ doped regions over the tunnel oxide layer, the N+ ions being implanted with a dose from about 1×

10¹⁵ /cm² to about 3×

10¹⁵ /cm².

4. A method in accordance with claim 3 wherein the implanting of N ions to form said PN junction is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV.

5. A method in accordance with claim 4 wherein

the resulting concentration of P dopant in the first polysilicon layer is from about 6×

10¹⁸ ions/cm³ to about 2×

10¹⁹ ions/cm³, and

the resulting concentration of N dopant in the first polysilicon layer is from about 6×

10¹⁹ ions/cm³ to about 2×

10²⁰ ions/cm³.

6. A method in accordance with claim 2 wherein the PN junction is formed by the further steps comprising

performing a first polysilicon layer P-type capacitor implant is performed into the first polysilicon layer with a blank-maskless P type implant of P- boron ions into the first polysilicon layer with a dose from about 1×

10¹⁴ /cm² to about 3×

10¹⁴ /cm², and

formation of a first polysilicon layer N-type capacitor implant photoresist mask with openings therein is formed upon the device followed by an N-type capacitor implant into portions of the first polysilicon layer through openings in the mask with an ion implant of N type ions selected from the group consisting of arsenic and phosphorus ions to form N+ doped regions over the tunnel oxide layer, the N+ ions being implanted with a dose from about 1×

10¹⁵ /cm² to about 3×

10¹⁵ /cm².

7. A method in accordance with claim 6 wherein the implanting of N ions to form said PN junction is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV.

8. A method in accordance with claim 7 wherein

the resulting concentration of P dopant in the first polysilicon layer is from about 6×

10¹⁸ ions/cm³ to about 2×

10¹⁹ ions/cm³, and

the resulting concentration of N dopant in the first polysilicon layer is from about 6×

10¹⁹ ions/cm³ to about 2×

10²⁰ ions/cm³.

9. A method in accordance with claim 6 wherein the PN junction implanting of N ions is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV, and

the resulting concentration of P dopant in the first polysilicon layer is from about 6×

10¹⁸ ions/cm³ to about 2×

10¹⁹ ions/cm³, and

the resulting concentration of N dopant in the first polysilicon layer is from about 6×

10¹⁹ ions/cm³ to about 2×

10²⁰ ions/cm³.

10. A method of forming a floating gate ROM device in accordance with claim 9 wherein the first polysilicon layer has a thickness from about 1.5 k Å

to about 2 k Å

.

11. A method of forming a floating gate ROM device comprising

forming a lightly doped P- semiconductor substrate,

forming a doped source region and a doped drain region in the substrate,

forming a tunnel oxide layer and field oxide regions over the surface of the substrate, a PN junction floating gate electrode comprising doped polysilicon with an N doped region above the tunnel oxide layer and at least one P doped region above the field oxide region juxtaposed with the N doped region,

forming an interpolysilicon ONO dielectric layer covering the PN floating gate electrode,

forming a polysilicon control gate electrode over the ONO dielectric layer,

forming an additional dielectric layer over the control gate electrode with a via opening down to the drain region, and

forming an electrical conductor over the additional dielectric layer extending down into the via opening into contact with the drain region.

12. A method in accordance with claim 11 wherein the PN junction is formed by the steps comprising

depositing a first polysilicon layer on the tunnel oxide layer and the field oxide regions,

performing a P-type capacitor implant into the first polysilicon layer,

forming a mask over the field oxide regions with openings over the tunnel oxide regions, and

performing a N-type capacitor implant into portions of the first polysilicon layer over the tunnel oxide regions through the openings in the mask.

13. A method in accordance with claim 11 wherein the PN junction is formed by the further steps comprising

performing a first polysilicon layer P-type capacitor implant is performed into the first polysilicon layer with a blank-maskless P type implant of P- boron ions into the first polysilicon layer with a dose from about 1×

10¹⁴ /cm² to about 3×

10¹⁴ /cm², and

formation of a first polysilicon layer N-type capacitor implant photoresist mask with openings therein is formed upon the device followed by an N-type capacitor implant into portions of the first polysilicon layer through openings in the mask with an ion implant of N type ions selected from the group consisting of arsenic and phosphorus ions to form type N+ doped regions over the tunnel oxide layer, the N+ ions being implanted with a dose from about 1×

10¹⁵ /cm² to about 3×

10¹⁵ /cm².

14. A method in accordance with claim 13 wherein the implanting of N ions to form said PN junction is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV.

15. A method in accordance with claim 14 wherein

the resulting concentration of P dopant in the first polysilicon layer is from about 6×

10¹⁸ ions/cm³ to about 2×

10¹⁹ ions/cm³, and

the resulting concentration of N dopant in the first polysilicon layer is from about 6×

10¹⁹ ions/cm³ to about 2×

10²⁰ ions/cm³.

16. A method in accordance with claim 12 wherein the PN junction is formed by the further steps comprising

performing a first polysilicon layer P-type capacitor implant is performed into the first polysilicon layer with a blank-maskless P type implant of P- boron ions into the first polysilicon layer with a dose from about 1×

10¹⁴ /cm² to about 3×

10¹⁴ /cm² and

formation of a first polysilicon layer N-type capacitor implant photoresist mask with openings therein is formed upon the device followed by an N-type capacitor implant into portions of the first polysilicon layer through openings in the mask with an ion implant of N type ions selected from the group consisting of arsenic and phosphorus ions to form N+ doped regions over the tunnel oxide layer, the N+ ions being implanted with a dose from about 1×

10¹⁵ /cm² to about 3×

10¹⁵ /cm².

17. A method in accordance with claim 16 wherein the implanting of N ions to form said PN junction is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV.

18. A method in accordance with claim 17 wherein

the resulting concentration of P dopant in the first polysilicon layer is from about 6×

10¹⁸ ions/cm³ to about 2×

10¹⁹ ions/cm³, and

the resulting concentration of N dopant in the first polysilicon layer is from about 6×

10¹⁹ ions/cm³ to about 2×

10²⁰ ions/cm³.

19. A method in accordance with claim 16 wherein the PN junction implanting of N ions is performed at an energy from about 70 keV to about 100 keV and the implanting of P ions is performed at an energy from about 30 keV to about 50 keV, and

the resulting concentration of P dopant in the first polysilicon layer is from about 6×

10¹⁹ ions/cm³ to about 2×

10¹⁹ ions/cm³, and

the resulting concentration of N dopant in the first polysilicon layer is from about 6×

10¹⁹ ions/cm³ to about 2×

10²⁰ ions/cm³.

20. A method of forming a floating gate ROM device in accordance with claim 19 wherein the first polysilicon layer has a thickness from about 1.5 k Å

to about 2 k Å

.