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Highly compact EPROM and flash EEPROM devices

  • US 5,554,553 A
  • Filed: 06/06/1995
  • Issued: 09/10/1996
  • Est. Priority Date: 06/08/1988
  • Status: Expired due to Term
First Claim
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1. A method of forming an array of flash EEPROM cells on a semiconductor substrate surface, comprising:

  • forming a plurality of parallel elongated source and drain regions beneath the substrate surface which have continuous lengths extending in a first direction across said surface and are spaced apart in a second direction thereacross to form channel regions therebetween, said first and second directions being substantially orthogonal to each other,forming a first plurality of parallel elongated conductive strips insulated from the substrate and individually positioned over at least a portion of a channel region with continuous lengths extending in said first direction and being spaced apart in the second direction,forming a second plurality of parallel elongated conductive strips as control gates insulated from the substrate and the first plurality of conductive strips, said second plurality of strips having continuous lengths extending in said second direction and being spaced apart in said first direction,removing a portion of said first strips through mask openings formed in spaces between said second strips with reference to edges of the second strips, thereby to convert the first strips into a two dimensional array of electrically isolated floating gates underlaying said second strips and exposing surface areas of the floating gates to the spaces between the second strips,forming tunnel dielectric layers on said exposed floating gate surface areas, andforming, in the spaces between said second strips in contact with said tunnel dielectric layers, a third plurality of parallel elongated conductive strips as erase gates with continuous lengths extending in said second direction and being spaced apart in the first direction, said third strips being insulated from the second strips and the substrate.

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