Highly compact EPROM and flash EEPROM devices

• US 5,554,553 A
• Filed: 06/06/1995
• Issued: 09/10/1996
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/467,762
• Time in Patent Office: 462 Days
• Field of Search: 437/43, 437/49, 437/48, 437/52, 257/320, 257/298, 365/182, 365/185.01, 365/185.33, 365/185.26
• US Class Current: 438/264
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 438/964 : Roughened surface

Abstract

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. A method of forming an array of flash EEPROM cells on a semiconductor substrate surface, comprising:

forming a plurality of parallel elongated source and drain regions beneath the substrate surface which have continuous lengths extending in a first direction across said surface and are spaced apart in a second direction thereacross to form channel regions therebetween, said first and second directions being substantially orthogonal to each other,

forming a first plurality of parallel elongated conductive strips insulated from the substrate and individually positioned over at least a portion of a channel region with continuous lengths extending in said first direction and being spaced apart in the second direction,

forming a second plurality of parallel elongated conductive strips as control gates insulated from the substrate and the first plurality of conductive strips, said second plurality of strips having continuous lengths extending in said second direction and being spaced apart in said first direction,

removing a portion of said first strips through mask openings formed in spaces between said second strips with reference to edges of the second strips, thereby to convert the first strips into a two dimensional array of electrically isolated floating gates underlaying said second strips and exposing surface areas of the floating gates to the spaces between the second strips,

forming tunnel dielectric layers on said exposed floating gate surface areas, and

forming, in the spaces between said second strips in contact with said tunnel dielectric layers, a third plurality of parallel elongated conductive strips as erase gates with continuous lengths extending in said second direction and being spaced apart in the first direction, said third strips being insulated from the second strips and the substrate.

2. The method according to claim 1 wherein removing a portion of the first strips includes etching the first strips through mask openings extending substantially completely across the spaces between adjacent ones of the second strips.

3. The method according to claim 1 wherein removing a portion of the first strips includes etching the first strips through mask openings formed in the spaces between adjacent ones of the second strips that are reduced in size by forming dielectric spacers along edges of said second strips in said spaces.

4. The method according to claim 1 wherein forming the first strips includes forming such strips with widths extending over only a portion of the channel regions in the second direction.

5. The method according to claim 1 wherein forming the third strips includes forming one of said third strips in substantially each of said spaces between the control gates.

6. The method according to claim 1 wherein forming the third strips includes contacting individual ones of the third strips with the dielectric layer carried by the floating gate surface areas on both sides of the spaces between the second strips.

7. The method according to claim 1 wherein forming the third strips includes extending the widths of individual ones of the third strips in said second direction over the second strips on opposite sides thereof.

8. The method according to claim 1 wherein removing a portion of said first strips in between the second strips includes removing less than all of the first strips therebetween, thereby to leave the floating gates extending into the spaces between the second strips.

9. The method according to claim 8 wherein forming the dielectric layer on the exposed surface areas of the floating gates includes forming said dielectric layer on top portions of the floating gates extending into the spaces between the second strips.

10. The method according to claim 1 wherein forming the source and drain regions in the substrate occurs after forming the first strips and by use of mask openings formed in spaces between said first strips that are referenced to edges of the first strips.

11. The method according to claim 10 wherein the mask openings are formed by the use of dielectric spacers formed along edges of the first strips.

12. The method according to any one of claims 1-11 wherein the first, second and third strips are formed along a straight line path with a substantially uniform width along their lengths through the array.

13. The method according to any one of claims 1-11 wherein forming the first, second and third plurality of conductive strips include forming respective first, second and third different layers of conductively doped polysilicon material.

14. A compact flash EEPROM cell array formed on a semiconductor substrate surface, comprising:

a plurality of continuous elongated conductively doped regions formed in the substrate with lengths extending in a substantially straight path in a first direction, said doped regions forming source and drain regions and being separated across the substrate surface in a second direction to form channel regions therebetween, said first and second directions being substantially orthogonal to each other,

a two dimensional array of rectangularly shaped floating gates arranged in substantially straight columns extending along the channel regions in the first direction and in substantially straight rows extending in the second direction,

a plurality of elongated control gates having lengths extending in substantially straight paths in said second direction and spaced apart in said first direction, individual ones of said control gates being positioned over individual ones of the rows of a plurality of floating gates with electrical insulation therebetween and in a manner that surfaces of the floating gates face spaces between the control gates,

a layer of tunnel dielectric carried by said floating gate surfaces, and

a plurality of elongated erase gates having lengths extending in said second direction in a substantially straight path and positioned in spaces between the control gates in the first direction in a manner to contact the layer of tunnel dielectric carried by the floating gate surfaces.

15. The flash EEPROM cell array of claim 14 wherein the floating gates are positioned over only a portion of the channel regions between adjacent doped regions in the second direction, thereby forming an array of split channel cells.

16. The flash EEPROM cell array of claim 14 wherein one of the erase gates is positioned in substantially each one of the spaces between the control gates in the first direction.

17. The flash EEPROM cell array of claim 16 wherein individual ones of the floating gates have two of said surfaces facing the spaces between the control gates on opposite sides of the floating gate, and wherein the tunnel dielectric carried by said opposing floating gate surfaces contact different erase gates.

18. The flash EEPROM cell array of claim 14 wherein said surfaces of the floating gates extend inward of the spaces between adjacent control gates.

19. The flash EEPROM cell array of claim 18 wherein said surfaces of the floating gates includes some areas on a top surface of the floating gates adjacent edges thereof within said spaces.

20. The flash EEPROM cell array of claim 14 wherein the erase gates have widths that extend in the first direction over adjacent ones of the control gates with electrical insulation therebetween.

21. The flash EEPROM cell array of claim 14 wherein the erase gates individually contact layers of tunnel dielectric on both sides of the individual spaces between the control gates.

22. The flash EEPROM cell array of any one of claims 14-21 wherein the floating, control and erase gates are formed from separate layers of conductively doped polysilicon material.