Power semiconductor device

• US 5,554,862 A
• Filed: 01/19/1994
• Issued: 09/10/1996
• Est. Priority Date: 03/31/1992
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakayama, Kazuya, Yamaguchi, Masakazu, Omura, Ichiro, Kitagawa, Mitsuhiko
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/183,364
• Time in Patent Office: 965 Days
• Field of Search: 257/133, 257/137, 257/138, 257/146, 257/163, 257/331, 257/332, 257/378
• US Class Current: 257/137
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.

Claims

1. A power semiconductor device comprising:

an emitter layer of a first conductivity type;

a base layer of a second conductivity type formed so as to be in contact with said emitter layer of said first conductivity type;

a low-resistance layer of said second conductivity type formed above said base layer of said second conductivity type and not in contact with said emitter layer of said first conductivity type, said low-resistance layer having a higher carrier concentration than that of said base layer of said second conductivity type;

an intermediate layer of said first conductivity type formed in a surface of said low-resistance layer of said second conductivity type;

a source layer of said second conductivity type formed in a surface of said intermediate layer of said first conductivity type;

a plurality of trenches formed in said low-resistance layer of said second conductivity type such that a side of each of said trenches is in contact with said intermediate layer of said first conductivity type and said source layer of said second conductivity type;

a gate electrode arranged within each of said trenches via a gate insulating film;

a first main electrode connected to said emitter layer of said first conductivity type; and

a second main electrode connected to said source layer of said second conductivity type,

wherein said low-resistance layer surrounds bottom portions of said trenches so as to completely separate said intermediate layer of said first conductivity type from said base layer of said second conductivity type.

2. The device according to claim 1, wherein said second main electrode is arranged to short-circuit said source layer of said second conductivity-type with said intermediate layer of said first conductivity-type.

3. The device according to claim 1, wherein said source layer of said second conductivity-type comprises a plurality of source layer portions separated from each other.

4. The device according to claim 3, wherein said intermediate layer of said first conductivity-type is in contact with said second main electrode between adjacent ones of said source layer portions such that said source layer portions and said base layer of said first conductivity-type are short-circuited.

5. The device according to claim 2, wherein a base layer of said first conductivity type is formed between said base layer of said second conductivity type and said low-resistance layer of said second conductivity type and is completely separated from said intermediate layer of said first conductivity type via said low-resistance layer of said second conductivity type, and wherein said device is operable as a thyristor.

6. The device according to claim 5, further comprising a MOSFET so as to selectively induce a channel of said first conductivity-type in said low-resistance layer of said second conductivity-type for connecting said base layer of said first conductivity-type and said intermediate layer of said first conductivity-type, said MOSFET including a gate electrode arranged via a gate insulating film within a trench which is formed in said low resistance layer of said second conductivity-type.

7. The device according to claim 2, further comprising a MOSFET so as to selectively induce a channel of said second conductivity-type in said low-resistance layer of said second conductivity-type for connecting said base layer of said second conductivity-type to said source layer of said second conductivity-type, said MOSFET including a gate electrode arranged via a gate insulating film in a trench which is formed in said low-resistance layer of said second conductivity-type.