Integrated circuit having both vertical and horizontal devices and process for making the same

• US 5,554,870 A
• Filed: 08/02/1995
• Issued: 09/10/1996
• Est. Priority Date: 02/04/1994
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Venkatesan, Suresh, Witek, Keith E., Fitch, Jon T.
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/510,329
• Time in Patent Office: 405 Days
• Field of Search: 257/331, 257/135, 257/330, 257/329, 257/334, 257/347, 257/350, 257/351
• US Class Current: 257/334
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

An integrated circuit (10) has a vertical device, such as a transistor (71), formed by epitaxial growth from a substrate (12) and a horizontal device, such as a transistor (73, 75) grown epitaxially from the vertical device. In accordance with one embodiment of the invention, all six transistors of an SRAM cell can be formed in single crystal material for improved device characteristics and increased cell density. Utilization of various combinations of vertical and horizontal devices permits a large degree of vertical integration within semiconductor devices.

Claims

1. An integrated circuit comprising:

a semiconductor substrate having a first active area formed of a single crystal semiconductor material;

a vertical device formed above the substrate and having a second active area vertically connected to the first active area, the vertical device having a first electrode and a second electrode within the second active area;

a dielectric layer formed above the substrate and adjacent at least a portion of the vertical device; and

a horizontal device formed above the substrate, on the dielectric layer, and connected to the substrate by the vertical device, the horizontal device having a third active area and a third electrode and a fourth electrode within the third active area;

wherein the first, second, third, and fourth electrodes are formed of a continuous single crystal semiconductor layer of the semiconductor material and are connected to each other, and wherein the first, second, third, and fourth electrodes have a same conductivity type.

2. The integrated circuit of claim 1 wherein the second electrode of the vertical device overlies the first electrode of the vertical device within the integrated circuit.

3. The integrated circuit of claim 2 wherein the vertical device is a field effect transistor and wherein the first and second electrodes of the vertical device are drain and source electrodes.

4. The integrated circuit of claim 3 wherein the horizontal device is a field effect transistor, and wherein the third electrode of the horizontal device is a current electrode.

5. The integrated circuit of claim 1 wherein the semiconductor substrate comprises single crystal silicon, and wherein the second and third active areas comprise epitaxial single crystal silicon.

6. The integrated circuit of claim 1 wherein the horizontal device is a first horizontal device and further comprising a second horizontal device, wherein the second horizontal device overlies the first horizontal device and has a fourth active area and a fifth electrode within the fourth active area, and wherein the fifth electrode is formed of the continuous single crystal semiconductor layer of the first, second, third, and fourth electrodes.

7. The integrated circuit of claim 1 wherein the vertical device is a first vertical device and further comprising a second vertical device having a fourth active area vertically connected to the first active area and having a fifth electrode within the fourth active area, and wherein the fifth electrode is formed of the continuous single crystal semiconductor layer of the first, second, third, and fourth electrodes.

8. The integrated circuit of claim 1 wherein the horizontal device is a first horizontal device, and further comprising a second horizontal device formed within the third active area and substantially planar with the first horizontal device.

9. The integrated circuit of claim 8 wherein the first and second horizontal devices are transistors.

10. The integrated circuit of claim 9 wherein the vertical transistor and first and second horizontal transistors are transistors of a static random access memory cell.

11. An integrated circuit comprising:

a substrate of a single crystal semiconducting material and having a first active area;

a vertical transistor formed above the substrate and comprising;

a second active area; and

a first and a second current electrode formed in the second active area, the second current electrode overlying the first current electrode, and the first and second current electrodes being separated by a channel region;

wherein the first current electrode is connected to the first active area;

a dielectric layer overlying the substrate and around at least a portion of the vertical transistor; and

a horizontal transistor formed above the substrate and comprising;

a third active area formed on the dielectric layer;

a first and a second current electrode formed in the third active area, positioned approximately horizontally to one another, and separated by a channel region;

wherein the first current electrode of the horizontal transistor is connected to the second current electrode of the vertical transistor such that a voltage on the first current electrode of the horizontal transistor is substantially equal to that on the second current electrode of the vertical transistor;

wherein the second and third active areas are formed of a continuous single crystal semiconductor segment.

12. The integrated circuit of claim 11 wherein the substrate is comprised of single crystal silicon, and wherein the second and third active areas each comprise epitaxial silicon.

13. The integrated circuit of claim 12 wherein the vertical transistor comprises:

a stack comprising a first dielectric layer, a polysilicon layer, and a second dielectric layer, wherein the second dielectric layer is the dielectric layer on which the third active area is formed, wherein a hole is formed through all layers of the stack to create a sidewall of the polysilicon layer;

a control electrode dielectric adjacent the sidewall of the polysilicon layer within the hole; and

a column of epitaxial silicon filling the hole, wherein a bottom portion of the column is the first current electrode, a top portion of the column is the second current electrode, and wherein the channel region lies between the top and bottom portions of the column;

wherein the polysilicon layer surrounding the hole serves as a control electrode of the vertical transistor.

14. The integrated circuit of claim 11 wherein the vertical transistor is a first vertical transistor, and further comprising a second vertical transistor formed above the substrate and comprising:

a fourth active area; and

a first and a second current electrode formed in the fourth active area, the second current electrode overlying the first current electrode, and the first and second current electrodes being separated by a channel region;

wherein the first current electrode of the second vertical transistor is connected to the first active area, and wherein the fourth active area is formed of the single crystal semiconducting material of the substrate.

15. The integrated circuit of claim 11 wherein the horizontal transistor is a first horizontal transistor, and further comprising a second horizontal transistor formed within the third active area.

16. The integrated circuit of claim 15 wherein the first and second horizontal transistors are formed on opposing sides of the vertical transistor.

17. The integrated circuit of claim 11 wherein the vertical transistor is a pass transistor and the horizontal transistor is a latch transistor in a static random access memory cell.

18. An integrated circuit comprising:

a semiconductor substrate having a first active area;

a dielectric layer having an opening formed therein, the opening having a central axis perpendicular to the semiconductor substrate;

a vertical transistor formed in a second active area above the substrate, within the opening in the dielectric layer, and connected to the first active area, the vertical transistor having a first current electrode, a second current electrode above the first current electrode, and a first channel region separating the first and the second current electrodes;

a first horizontal transistor formed in a third active area on the dielectric layer and connected to the second active area, the first horizontal transistor extending in a first direction approximately perpendicular to the central axis of the opening and having a third current electrode, a fourth current electrode, and a second channel region separating the third and the fourth current electrodes; and

a second horizontal transistor formed in the third active area on the dielectric layer, the second horizontal transistor extending in a second direction approximately perpendicular to the central axis of the opening, and having a fifth current electrode, a sixth current electrode, and a third channel region separating the fifth and the sixth current electrodes.

19. The integrated circuit of claim 18 wherein the first and the second horizontal transistors are substantially co-planar.

20. The integrated circuit of claim 18 wherein the first direction is approximately opposite the second direction.

21. The integrated circuit of claim 18 wherein the first channel region and the second channel region are offset from the opening in the dielectric.

22. An integrated circuit comprising:

a single crystal semiconductor substrate having a first active area;

a dielectric layer formed over the semiconductor substrate, the dielectric layer having a vertical sidewall and a top surface which meets the vertical sidewall;

a vertical transistor formed above the semiconductor substrate, having a second active area vertically connected to the first active area, and being adjacent the vertical sidewall of the dielectric layer, the vertical transistor having a first electrode and a second electrode within the second active area;

a horizontal transistor formed in a third active area connected to the second active area, the horizontal transistor having a third electrode, a fourth electrode, and a channel region separating the third electrode and the fourth electrode, wherein the third electrode, the;

fourth electrode, and the channel region are formed on the top surface of the dielectric layer such that the channel region is offset from the vertical sidewall of the dielectric layer wherein the second and third active areas are formed of a continuous single crystal semiconductor segment.