Six-transistor cell with wide bit-line pitch, double words lines, and bit-line contact shared among four cells
First Claim
1. An integrated circuit static random-access memory comprising:
- a substrate of semiconductor material of a first conductivity type;
an array of memory cells fabricated in the substrate, the cells arranged in rows and columns;
each memory cell in the array of memory cells comprising;
a cross-coupled pair of inverters for storing one bit of data, a first inverter having a first n-channel pull-down transistor and a second inverter having a second n-channel pull-down transistor, each n-channel transistor having a drain diffusion and a gate;
a first access transistor, having a drain diffusion electrically coupled to the drain diffusion of the first n-channel pull-down transistor and electrically coupled to the gate of the second n-channel pull-down transistor of the cross-coupled pair of inverters, the first access transistor having a source diffusion and a gate;
a second access transistor, having a drain diffusion electrically coupled to the drain diffusion of the second n-channel pull-down transistor and electrically coupled to the gate of the first n-channel pull-down transistor of the cross-coupled pair of inverters, the second access transistor having a source diffusion and a gate;
the drain diffusion of the first access transistor being formed in common with the drain diffusion of the first n-channel pull-down transistor, and the drain diffusion of the second access transistor being formed in common with the drain diffusion of the second n-channel pull-down transistor;
the array having a group of four cells of the memory cells disposed in a mutually contiguous relation to each other in a first row and in a second row adjacent to the first row, and in a first column and in a second column adjacent to the first column; and
the source diffusions of the first access transistors of each cell in the group of four cells being formed in common in a common diffusion area, the first access transistors of the group of four cells being electrically and physically connected to each other by the common diffusion area and not by a metal layer;
whereby the first access transistor in each cell in the group of four cells shares the common diffusion area.
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Accused Products
Abstract
A static RAM memory is arranged into groups of four cells sharing a single active region with a contact to one of the bit lines. The shared active region forms the sources of four access transistors. The group of four cells requires only one pair of bit lines instead of the usual two pairs of bit lines. Thus a pair of bit lines occurs for every two cells rather than for every cell. This increases the bit-line pitch and facilitates design and layout of the sense amps. Since only one of the four cells can drive the bit lines at any time, four word lines are used instead of only two. Each cell has two word lines crossing over it, and the cells in a row alternately connect to one or the other word line. Since word-line drivers and decoders are simpler and easier to lay out than the sense amps, the tighter word-line pitch is acceptable. An unused metal line occurs for every two columns of cells. The bit lines are shielded from this unused metal line by power and ground lines. Thus the shielded metal line is ideal for system interconnect through the RAM when the RAM is embedded in a larger system.
48 Citations
20 Claims
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1. An integrated circuit static random-access memory comprising:
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a substrate of semiconductor material of a first conductivity type; an array of memory cells fabricated in the substrate, the cells arranged in rows and columns; each memory cell in the array of memory cells comprising; a cross-coupled pair of inverters for storing one bit of data, a first inverter having a first n-channel pull-down transistor and a second inverter having a second n-channel pull-down transistor, each n-channel transistor having a drain diffusion and a gate; a first access transistor, having a drain diffusion electrically coupled to the drain diffusion of the first n-channel pull-down transistor and electrically coupled to the gate of the second n-channel pull-down transistor of the cross-coupled pair of inverters, the first access transistor having a source diffusion and a gate; a second access transistor, having a drain diffusion electrically coupled to the drain diffusion of the second n-channel pull-down transistor and electrically coupled to the gate of the first n-channel pull-down transistor of the cross-coupled pair of inverters, the second access transistor having a source diffusion and a gate; the drain diffusion of the first access transistor being formed in common with the drain diffusion of the first n-channel pull-down transistor, and the drain diffusion of the second access transistor being formed in common with the drain diffusion of the second n-channel pull-down transistor; the array having a group of four cells of the memory cells disposed in a mutually contiguous relation to each other in a first row and in a second row adjacent to the first row, and in a first column and in a second column adjacent to the first column; and the source diffusions of the first access transistors of each cell in the group of four cells being formed in common in a common diffusion area, the first access transistors of the group of four cells being electrically and physically connected to each other by the common diffusion area and not by a metal layer; whereby the first access transistor in each cell in the group of four cells shares the common diffusion area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory comprising:
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a plurality of memory cells arranged in an array of rows and columns, a row and a column intersecting at a single cell, the columns being further arranged into non-overlapping column-pairs each consisting of two adjacent columns; a first and a second word line for each row of memory cells, the first word line selecting a first plurality of memory cells in the row and the second word line selecting a second plurality of memory cells in the row, each memory cell in the first plurality of cells being adjacent on both sides to memory cells in the second plurality of cells in an alternating sequence memory cells in the row of memory cells; a pair of bit lines for every column-pair of memory cells, the pair of bit lines including a true bit line and a complement bit line together communicating one bit of data; each cell in the plurality of memory cells comprising;
storage means for storing one bit of data;
first access transistor means for coupling the storage means to the true bit line; andsecond access transistor means for coupling the storage means to the complement bit line; the first and the second access transistor means having control gates coupled to a local word line for the cell, the local word line being coupled to the first word line when the cell is in the first plurality of cells but coupled to the second word line when the cell is in the second plurality of cells; whereby each memory cell connects to one of the two word lines crossing the cell and one pair of bit lines connects to two columns of cells. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification