Voltage controlled phase shifter with unlimited range

• US 5,554,945 A
• Filed: 02/15/1994
• Issued: 09/10/1996
• Est. Priority Date: 02/15/1994
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Lee, Thomas H., Donnelly, Kevin S., Ho, Tsyr-Chyang
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/196,582
• Time in Patent Office: 938 Days
• Field of Search: 327/231-238, 327/105, 327/355, 327/356, 327/357, 327/359, 327/250, 327/254, 327/256, 327/255, 327/107, 327/257, 327/266, 327/274, 327/280, 455/333
• US Class Current: 327/105
• CPC Class Codes: H03H 11/20 Two-port phase shifters providing an adjustable phase shift
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency

Abstract

A voltage-controlled phase shift apparatus having an unlimited range for producing an output signal that varies in phase from an input signal by a predetermined phase difference. The phase shift apparatus includes a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is α degrees out of phase with the input signal, a second intermediate signal that is β degrees out of phase with the first intermediate signal, a third intermediate signal that is 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 180 degrees out of phase with the second intermediate signal. The phase shift apparatus also includes a phase interpolator circuit coupled to receive a control voltage signal and the first, second, third and fourth intermediate signals, the phase interpolator for phase mixing a selected pair of the first, second, third and fourth intermediate signals in response to the control voltage signal, the phase interpolator for outputting the output signal. A phase selector circuit coupled to the phase interpolator circuit and coupled to receive a phase slope signal and the control voltage signal selects the selected pair in response to the phase slope signal and the control voltage signal such that the output signal varies in phase from the input signal by the predetermined phase difference.

Claims

1. A phase shift apparatus for producing an output signal that varies in phase from an input signal by a predetermined phase difference in response to a control voltage, the phase shift apparatus comprising:

a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is α

degrees out of phase with the input signal and a second intermediate signal that is β

degrees out of phase with the first intermediate signal; and

a phase interpolator circuit coupled to receive the control voltage signal, the first intermediate signal, and the second intermediate signal, the phase interpolator for phase mixing the first and second intermediate signals in response to the control voltage signal to produce the output signal such that an output vector representative of the output signal is a sum of a first fraction of a first vector representative of the first intermediate signal and a second fraction of a second vector representative of the second intermediate signal, wherein the control voltage is a differential voltage VC+ and VC-, the phase interpolator comprising;

a first transistor including a first terminal for receiving a supply current, a second terminal for dispensing the supply current, and a third terminal for controlling the amount of supply current flowing from the first terminal to the second terminal in response to VC+;

a second transistor including a first terminal for receiving a supply current, a second terminal for dispensing the supply current, and a third terminal for controlling the amount of supply current flowing from the first terminal of the second transistor to the second terminal of the second transistor in response to VC-;

a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to system ground;

a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to system ground;

a comparator having a negative input coupled to the second terminal of the first capacitor and a positive input coupled to the second terminal of the second capacitor, the comparator for outputting the output voltage;

a phase mixer circuit including a first input coupled to the second terminal of the first transistor, a second input coupled to the second terminal of the second transistor, a first output coupled to the second terminal of the first capacitor, and a second output coupled to the second terminal of the second capacitor, the phase mixer circuit for coupling and decoupling the first input to the first output in response to the first intermediate signal, and for coupling and decoupling the second input to the second output in response to the second intermediate signal.

2. A phase shift apparatus for producing an output signal that varies in phase from an input signal by a predetermined phase difference in response to a control voltage, the phase shift apparatus comprising:

a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is α

degrees out of phase with the input signal, a second intermediate signal that is β

degrees out of phase with the first intermediate signal, a third intermediate signal that is 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 180 degrees out of phase with the second intermediate signal;

a phase interpolator circuit coupled to receive a control voltage signal and the first, second, third and fourth intermediate signals, the phase interpolator for phase mixing a selected pair of the first, second, third and fourth intermediate signals in response to the control voltage signal to produce the output signal such that an output vector representative of the output signal is a sum of fractions of vectors representative of each selected intermediate signal of the selected pair; and

a phase selector circuit coupled to the phase interpolator circuit and coupled to receive a phase slope signal and the control voltage signal, the phase selector circuit for selecting the selected pair in response to the phase slope signal and the control voltage signal such that the output signal varies in phase from the input signal by the predetermined phase difference, wherein the phase selector circuit includes;

a quadrant boundary detector for outputting a MAX signal when the control voltage is at a maximum voltage level and a MIN signal when the control voltage is at a minimum voltage level, the MAX and MIN signals indicating when a weighted fraction for a selected intermediate signal of the first selected pair is equal to zero;

a phase selector state machine coupled to receive the MAX signal, the MIN signal and the phase slope signal, the phase selector for selecting the selected pair in response to the MAX signal, the MIN signal and the phase slope signal by asserting as active two of a plurality of select signals, said plurality of select signals including an ISEL signal, an ISELB signal, a QSEL signal and a QSELB signal.

3. The phase shift apparatus of claim 2, wherein the control voltage is a differential voltage VC+ and VC-, the phase interpolator comprising:

a first transistor including a first terminal for receiving a supply current, a second terminal for dispensing the supply current, and a third terminal for controlling the amount of supply current flowing from the first terminal of the first transistor to the second terminal of the first transistor in response to VC+;

a second transistor including a first terminal for receiving a supply current, a second terminal for dispensing the supply current, and a third terminal for controlling the amount of supply current flowing from the first terminal of the second transistor to the second terminal of the second transistor in response to VC-;

a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to system ground;

a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to system ground;

a comparator having a negative input coupled to the second terminal of the first capacitor and a positive input coupled to the second terminal of the second capacitor, the comparator for outputting the output voltage;

a phase mixer circuit coupled to receive the plurality of select signals and the intermediate signals, the phase mixer circuit including a first input coupled to the second terminal of the first transistor, a second input coupled to the second terminal of the second transistor, a first output coupled to the second terminal of the first capacitor, and a second output coupled to the second terminal of the second capacitor, the phase mixer circuit for coupling and decoupling the first input to the first output in response to a selected one of the first and third intermediate signals, and for coupling and decoupling the second input to the second output in response to a selected one of the second and fourth intermediate signals.

4. The phase shift apparatus of claim 3, wherein the phase mixer circuit couples and decouples the first input to the second output in response to the third intermediate signal when the first intermediate signal is selected to couple and decouple the first input to the first output.

7. The phase shift apparatus of claim 3, wherein the phase mixer circuit couples and decouples the first input to the second output in response to the third intermediate signal when the first intermediate signal is selected to couple and decouple the first input to the first output.

5. A phase shift apparatus for producing an output signal that varies in phase from an input signal by a predetermined phase difference in response to a control voltage, the phase shift apparatus comprising:

a delay circuit coupled to receive the input signal, the delay circuit for outputting a first intermediate signal, a second intermediate signal that is 90 degrees out of phase with the first intermediate signal, a third intermediate signal that 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 270 degrees out of phase with the first intermediate signal, the delay circuit including a frequency divider circuit for dividing an input frequency of the input signal in half such that a intermediate frequency of the first, second, third and fourth intermediate signals is equal to half of the input frequency;

a first phase interpolator circuit coupled to receive a control voltage signal and the first, second, third and fourth intermediate signals, the first phase interpolator for phase mixing a first selected pair of the first, second, third and fourth intermediate signals in response to the control voltage signal to produce a first output signal such that an output vector representative of the first output signal is a sum of fractions of vectors representative of each selected intermediate signal of the first selected pair;

a second phase interpolator circuit coupled to receive a control voltage signal and the first, second, third and fourth intermediate signals, the second phase interpolator for phase mixing a second selected pair of the first, second, third and fourth intermediate signals in response to the control voltage signal to produce a second output signal that is 90 degrees out of phase with the first output signal such that a phase of the second output signal is a sum of weighted fractions of each phase of the selected intermediate signals of the second selected pair;

a frequency doubler circuit coupled to receive the first output signal and the second output signal, the frequency doubler circuit for generating the output signal in response to the first and second output signals, the output signal having an output frequency equal to the input frequency; and

a phase selector circuit coupled to the first phase interpolator circuit and coupled to receive a phase slope signal and the control voltage signal, the phase selector circuit for selecting the first and second selected pairs in response to the phase slope signal and the control voltage signal such that the output signal varies in phase from the input signal by the predetermined phase difference, wherein the phase selector circuit includes;

a quadrant boundary detector for outputting a MAX signal when the control voltage is at a maximum voltage level and a MIN signal when the control voltage is at a minimum voltage level, the MAX and MIN signals indicating when a weighted fraction for a selected intermediate signal of the first selected pair is equal to zero;

a phase selector state machine coupled to receive the MAX signal, the MIN signal and the phase slope signal, the phase selector for selecting the selected pair in response to the MAX signal, the MIN signal and the phase slope signal by asserting as active two of a plurality of select signals, said plurality of select signals including an ISEL signal, an ISELB signal, a QSEL signal and a QSELB signal.

6. The phase shift apparatus of claim 5, wherein the control voltage is a differential voltage VC+ and VC-, the first phase interpolator comprising:

a first transistor including a first terminal for receiving a supply current, a second terminal for dispensing the supply current, and a third terminal for controlling the amount of supply current flowing from the first terminal of the first transistor to the second terminal of the first transistor in response to VC+;

a second transistor including a first terminal for receiving a supply current, a second terminal for dispensing the supply current, and a third terminal for controlling the amount of supply current flowing from the first terminal of the second transistor to the second terminal of the second transistor in response to VC-;

a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to system ground;

a second capacitor having a first terminal and a second terminal, wherein the first terminal Of the second capacitor is coupled to system ground;

a comparator having a negative input coupled to the second terminal of the first capacitor and a positive input coupled to the second terminal of the second capacitor, the comparator for outputting the output voltage;

a phase mixer circuit including a first input coupled to the second terminal of the first transistor, a second input coupled to the second terminal of the second transistor, a first output coupled to the second terminal of the first capacitor, and a second output coupled to the second terminal Of the second capacitor, the phase mixer circuit for coupling and decoupling the first input to the first output in response to a selected one of the first and third intermediate signals, and for coupling and decoupling the second input to the second output in response to a selected one of the second and fourth intermediate signals.

8. A phase shift circuit comprising:

a differential amplifier including a pair of inputs and a pair of outputs, the pair of inputs being coupled to receive differential control voltage VC- and VC+;

a phase mixer including a first pair of inputs coupled to the outputs of the differential amplifier, a second pair of inputs coupled to a pair of quadrature signals, a first output, and a second output, the phase mixer providing current supplied by the outputs of the differential amplifier to the first and second outputs in response to the pair of quadrature signals;

a first capacitive element coupled between ground and the first output of the phase mixer;

a second capacitive element coupled between ground the second output of the phase mixer; and

a comparator having a first input coupled to the first output of the phase mixer and a second input coupled to the second output of the phase mixer, wherein the comparator outputs a phase shifted signal in response to the first and second capacitive elements being charged and discharged by the phase mixer.

9. The phase shift circuit of claim 8, wherein the pair of quadrature signals are selected from a group of signals that are 0°

, 90°

, 180°

, and 270°

out of phase with a reference signal.

10. The phase shift circuit of claim 8, wherein the differential amplifier comprises:

a first transistor including a gate coupled to differential control voltage VC+, a drain, and a source coupled between a common node and a first supply voltage wherein the drain of first transistor is coupled as one of the pair of outputs;

a first current source load coupled between the drain of the first transistor and the first supply voltage;

a second transistor including a gate coupled to differential control voltage VC-, a drain, and a source coupled to the common node wherein the drain of the second transistor is coupled as another of the pair of outputs;

a second current source load coupled between the drain of the second transistor and the first supply voltage; and

a third current source coupled between the common node and a second supply voltage.