Digital to analog coverter having multiple resistor ladder stages

• US 5,554,986 A
• Filed: 05/03/1994
• Issued: 09/10/1996
• Est. Priority Date: 05/03/1994
• Status: Expired due to Term

• Current Assignee: Unitrode Corp. (Texas Instruments, Inc.)
• Original Assignee: Unitrode Corp. (Texas Instruments, Inc.)
• Inventors: Neidorff, Robert A.
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/237,388
• Time in Patent Office: 861 Days
• Field of Search: 341/145, 341/146, 341/148, 341/153
• US Class Current: 341/145
• CPC Class Codes: H03M 1/682 both converters being of the unary decoded type
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals
• CPC Class Codes: H03M 1/808 using resistors

Abstract

A multi-stage digital to analog converter with increased speed and enhanced accuracy. Multiple resistor ladders are interconnected through switches with the first resistor ladder converting the most significant bits and successive ladders converting lesser significant bits. The resistance values of the resistors of each ladder are greater than those of the preceding ladders in order to minimize inaccuracies due to loading. A monolithic fabrication technique includes a common resistor biasing scheme to switch the voltage across parasitic capacitances associated with the resistors in each ladder in common mode, thereby increasing the converter speed.

Claims

1. A digital to analog converter comprising:

a first resistor ladder comprising a first plurality of resistors coupled in series, said first resistor ladder being coupled across a supply voltage;

a second resistor ladder comprising a second plurality of resistors coupled in series, wherein each of said second plurality of resistors has a higher resistance value than each of said first plurality of resistors;

a plurality of switches coupled between said first resistor ladder and said second resistor ladder; and

a decoder responsive to a digital input signal for controlling said plurality of switches so as to provide an analog output signal across a portion of said second resistor ladder having a value corresponding to said digital input signal.

2. The digital to analog converter recited in claim 1 wherein a first portion of said plurality of switches has first terminals coupled to said first resistor ladder and second terminals coupled to a top one of said second plurality of resistors of said second resistor ladder and wherein a second portion of said plurality of switches has first terminals coupled to said first resistor ladder and second terminals coupled to a bottom one of said second plurality of resistors of said second resistor ladder.

3. The digital to analog converter recited in claim 1 wherein said plurality of switches are FETs.

4. The digital to analog converter recited in claim 1 wherein each resistor of said first resistor ladder is comprised of polycrystalline silicon and each resistor of said second resistor ladder is a diffusion resistor.

5. A digital to analog converter comprising:

a first resistor ladder having a top node and a bottom node and comprising a first plurality of resistors coupled in series, said top and bottom nodes being coupled across a supply voltage;

a second resistor ladder having a top node and a bottom node and comprising a second plurality of resistors coupled in series, wherein each of said second plurality of resistors has a higher resistance value than each of said first plurality of resistors;

a plurality of switches coupled between said first resistor ladder and said second resistor ladder, wherein a first portion of said plurality of switches has first terminals coupled to said first resistor ladder and second terminals coupled to said top node of said second resistor ladder and wherein a second portion of said plurality of switches has first terminals coupled to said first resistor ladder and second terminals coupled to said bottom node of said second resistor ladder such that each junction between two adjacent ones of said first plurality of resistors of said first resistor ladder is coupled to one of said first terminals of said first portion of said plurality of switches and to one of said first terminals of said second portion of said plurality of switches; and

a decoder responsive to a digital input signal for controlling said plurality of switches so as to provide an analog output signal across a portion of said second resistor ladder having a value corresponding to said digital input signal.

6. The digital to analog converter recited in claim 5 wherein said plurality of switches are FETs.

7. The digital to analog converter recited in claim 5 wherein each of said first plurality of resistors is comprised of polycrystalline silicon and each of said second plurality of resistors is a diffusion resistor.

8. A monolithic digital to analog converter comprising:

a resistor ladder comprising a plurality of integrated circuit resistors coupled in series, wherein each of said resistors is biased to a common substrate.

9. The digital to analog converter recited in claim 8 further comprising a preceding resistor ladder comprising a second plurality of resistors coupled in series, said preceding resistor ladder being coupled across a supply voltage, and a plurality of switches coupled between said resistor ladder and said preceding resistor ladder.

10. The digital to analog converter recited in claim 9 wherein each resistor of said resistor ladder is a diffusion resistor and each resistor of said preceding resistor ladder is comprised of polycrystalline silicon.

11. A integrated circuit digital to analog converter comprising:

a first resistor ladder comprising a first plurality of resistors coupled in series and comprising polycrystalline silicon, said first resistor ladder being coupled across a supply voltage;

a second resistor ladder comprising a second plurality of resistors coupled in series and having a pair of input nodes, wherein each of said second plurality of resistors is a diffusion resistor having a greater resistance value than each of said first plurality of resistors;

a plurality of switches coupled between said first resistor ladder and said pair of input nodes of said second resistor ladder; and

a decoder responsive to a digital input for controlling said plurality of switches so as to provide an analog output signal across a portion of said second resistor ladder having a value corresponding to said digital input signal.

12. The converter recited in claim 11 wherein each of said diffusion resistors comprises a doped silicon region disposed in a common well, wherein said well is biased to the potential of one of said input nodes of said second resistor ladder.

13. The converter recited in claim 11 wherein each of said plurality of switches comprises a FET.

14. A digital to analog converter comprising:

a decoder responsive to a digital word comprising a plurality of bits for providing a switch control signal; and

a plurality of stages, each stage having a pair of input nodes and a pair of output nodes and converting a corresponding plurality of said bits of said digital word into an analog voltage, wherein each one of said plurality of stages comprises;

(a) a resistor ladder coupled across said pair of input nodes; and

(b) a plurality of switches coupled between said resistor ladder and said pair of output nodes and controlled by said switch control signal, wherein said pair of output nodes of at least one of said plurality of stages is coupled to said pair of input nodes of a succeeding one of said plurality of stages and said pair of output nodes of at least one of said plurality of stages is coupled to an output terminal of said converter, wherein each resistor of said resistor ladder of a succeeding stage has a higher resistance value than each resistor of said resistor ladder of a preceding stage.

15. A digital to analog converter comprising:

a first resistor ladder having a top node and a bottom node and comprising a first plurality of resistors coupled in series, said top and bottom nodes being coupled across a supply;

a second resistor ladder having a top node and a bottom node and comprising a second plurality of integrated circuit resistors, each one coupled to a common substrate, wherein each of said second plurality of resistors has a higher resistance value than each of said first plurality of resistors;

a plurality of switches coupled between said first resistor ladder and said second resistor ladder, a first portion of said plurality of switches having first terminals coupled to said first resistor ladder and second terminals coupled to said top node of said second resistor ladder and a second portion of said plurality of switches having first terminals coupled to said first resistor ladder and second terminals coupled to said bottom node of said second resistor ladder, wherein said common substrate is coupled to said top node of said first resistor ladder; and

a decoder responsive to a digital input signal for controlling said plurality of switches so as to provide an analog output signal across a portion of said second resistor ladder having a value corresponding to said digital input signal.

16. The digital to analog converter recited in claim 15 wherein each of said plurality of switches comprises an NMOS FET.

17. The digital to analog converter recited in claim 15 wherein each of said plurality of switches comprises a PMOS FET and an NMOS FET coupled in parallel.