Method and apparatus for redundancy word line replacement in a semiconductor memory device

• US 5,555,212 A
• Filed: 09/19/1994
• Issued: 09/10/1996
• Est. Priority Date: 09/19/1994
• Status: Expired due to Term

• Current Assignee: International Business Machines SA (International Business Machines Corporation), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: International Business Machines Corporation, Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Toshiaki, Kirihata, Daisuke, Kato
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/306,438
• Time in Patent Office: 722 Days
• Field of Search: 365/200, 365/201, 365/149, 365/225.7, 371/10.1, 371/10.2, 371/10.3
• US Class Current: 365/200
• CPC Class Codes: G11C 29/84 with improved access time or stability

Abstract

A method and apparatus for redundancy word line replacement in a semiconductor device involves generating a control signal which causes the data on the data lines to be flipped when the bit pattern of the memory cells coupled to a redundant word line are complementary to the bit pattern of the memory cells of a defective word line which is being replaced by the redundant word line. During both read and write operations, a data flip control signal is input to a data flip circuit to control the state of the bit information.

Claims

1. A semiconductor memory device, comprising:

memory cells arranged in rows and columns, said memory cells including normal memory cells and redundant memory cells for replacing defective ones of said normal memory cells;

bit line pairs connected to said memory cells, each bit line pair consisting of first and second bit lines which are respectively connected to memory cells for storing true data and memory cells for storing complementary data in corresponding ones of said columns;

word lines, said word lines including normal word lines each respectively connected to normal memory cells in a corresponding one of said rows and redundant word lines each respectively connected to redundant memory cells in a corresponding one of said rows, said normal word lines including a first normal word line for selecting a first normal memory cell for storing true data connected to the first bit line of one of said bit line pairs and a second normal word line for selecting a second normal memory cell for storing complementary data connected to the second bit line of said one of said bit line pairs, and said redundant word lines including a first redundant word line for selecting a first redundant memory cell for storing true data connected to the first bit line of said one of said bit line pairs and a second redundant word line for selecting a second redundant memory cell for storing complementary data connected to the second bit line of said one of said bit line pairs;

a data line pair consisting of first and second data lines for inputting/outputting complementary data signals to/from said bit line pairs;

a data flip circuit for selectively flipping the data signals on said first and second data lines; and

redundancy control means for controlling said data flip circuit to flip the data signals on said first and second data lines when said first normal memory cell connected to said first normal word line is replaced with said second redundant memory cell connected to said second redundant word line or when said second normal memory cell connected to said second normal word line is replaced with said first redundant memory cell connected to said first redundant word line.

2. The semiconductor memory device according to claim 1, further comprising:

sense amplifiers each respectively connected to a corresponding one of said bit line pairs for amplifying a potential difference between said first and second bit lines of the respectively corresponding one of said bit line pairs.

3. The semiconductor device according to claim 1, wherein said redundancy control means includes a decoder for generating a data flip control signal, said decoder supplying the data flip control signal to said data flip circuit wherein the data flip circuit flips the data signals according to the data flip control signal.

4. The semiconductor memory device according to claim 3, wherein said data flip circuit includes a data input buffer for receiving a data input bit, the data input bit being flipped when the data flip control signal is active during a write operation, and supplying a representation of the flipped or unflipped data input bit to said first and second data lines.

5. The semiconductor memory device according to claim 3, wherein said data flip circuit includes a data output buffer, coupled to said first and second data lines, which receives a data output bit representing bit information on said first and second data lines, the data output bit being flipped when the data flip control signal is active during a read operation, and reading out one of the flipped or unflipped data output bit.

6. The semiconductor memory device according to claim 3, wherein the data flip circuit responsive to a first level of the data flip control signal flips the data signals on said first and second data lines when said first memory cell connected to said first normal word line is replaced with said second redundant memory cell connected to said second redundant word line or when said second normal memory cell connected to second normal word line is replaced with said first redundant memory cell connected to said first redundant word line, or the data flip circuit responsive to a second level of the data flip control signal does not flip the data signals on said first and second data lines when said first normal memory cell connected to said first normal word line is replaced with said first redundant memory cell connected to said first redundant word line or when said second normal memory cell connected to said second normal word line is replaced with said second redundant memory cell connected to said second redundant word line.

7. The semiconductor memory device according to claim 3, wherein said decoder receives an address of one of said first or second normal memory cells to be accessed and generates a redundant word line drive signal to drive one of said first or second redundant word lines to access one of said first or second redundant memory cells to replace said one of said first or second normal memory cells when said one of said first or second normal memory cells is defective, said decoder generating the data flip control signal according to whether said one of said first or second normal memory cells and said one of said first or second redundant memory cells both store true or complementary data.

8. The semiconductor memory device according to claim 7, wherein if said one of said first or second normal memory cells and said one of said first or second redundant memory cells both store true or complementary data, the data flip control signal is in a non-flip state wherein the data signals are not flipped, and if said one of said first or second normal memory cells and said one of said first or second redundant memory cells do not both store true or complementary data the data flip control signal is in a flip state wherein the data signals are flipped.

9. The semiconductor memory device according to claim 7, wherein said decoder includes a comparator circuit for determining whether the received normal memory cell address corresponds to a defective memory cell address, said comparator circuit generating the redundant word line drive signal when the received normal memory cell address corresponds to the defective memory cell address.

10. A semiconductor memory device, comprising:

a plurality of normal and redundant memory cells connected to word lines and bit lines, a first group of said word lines coupled to normal and redundant memory cells having a first bit pattern and a second group of said word lines coupled to normal and redundant memory cells having a second bit pattern different from said first bit pattern;

first and second data lines, said first data line being coupled to a first group of bit lines and said second data line being coupled to a second group of said bit lines;

a data flip circuit for flipping data signals on said first and second data lines when a normal memory cell coupled to said second group of word lines is coupled to said data lines and when a redundant memory cell coupled to said second group of word lines is coupled to said data lines.

11. The semiconductor memory device according to claim 10, further comprising:

a decoder for generating a data flip control signal, said decoder supplying the data flip control signal to said data flip circuit wherein the data flip circuit flips said data signals according to the data flip control signal.

12. The semiconductor memory device according to claim 11, wherein said decoder receives a memory cell address and includes a logic circuit for generating the data flip control signal by determining whether the received memory cell address is from said first group or said second group of said word lines.

13. The semiconductor memory device according to claim 10, wherein the first bit pattern is complementary to the second bit pattern.

14. The semiconductor memory device according to claim 10, wherein the same physical data can be stored in all the normal memory cells and all the redundant memory cells.

15. A method for testing a semiconductor memory device comprising the steps of:

inputting identical data signals to true bit pattern memory cells and complementary bit pattern memory cells;

accessing the data signals from the true bit pattern memory cells and the complementary bit pattern memory cells;

flipping the data signals accessed from the complementary bit pattern memory cells; and

determining whether the flipped data signals and the data signals accessed from the true bit pattern memory cells are the same, wherein if the flipped data signals and the data signals accessed from the true bit pattern memory cells are not the same a defective memory cell has been detected.

16. A semiconductor memory device with row redundancy comprising:

bit line pairs each consisting of a first bit line and a second bit line;

a first normal word line for selecting a first normal memory cell for storing true data connected to said first bit line of one of said bit line pairs;

a second normal word line for selecting a second normal memory cell for storing complementary data connected to said second bit line of said one of said bit line pairs;

a first redundant word line for selecting a first redundant memory cell for storing true data connected to said first bit line of said one of said bit line pairs;

a second redundant word line for selecting a second redundant memory cell for storing complementary data connected to said second bit line of said one of said bit line pairs;

a data line pair consisting of a first data line and a second data line, said data line pair transferring data signals to/from one of said normal memory cells or one of said redundant memory cells via said first and second bit lines;

a data flip circuit for selectively flipping the data signals on said first and second data lines; and

redundancy control means for controlling said data flip circuit to flip the data signals on said first and second data lines when said first normal memory cell connected to said first normal word line is replaced with said second redundant memory cell connected to said second redundant word line or when said second normal memory cell connected to said second normal word line is replaced with said first redundant memory cell connected to said first redundant word line.

17. The semiconductor memory device according to claim 16, further comprising:

sense amplifiers, each connected to a corresponding one of said bit line pairs, for amplifying the data signals on said bit line pairs; and

I/O gates for selecting one of said bit line pairs.

18. The semiconductor memory device according to claim 17, further comprising a column decoder for decoding a column address signal to control said I/O gates to select one of said bit line pairs.

19. The semiconductor memory device according to claim 16, further comprising:

a row decoder for decoding a row address signal and generating a word line selection signal;

a word line driver, responsive to a first word line driving signal from said redundancy control means, for driving said first and second normal word lines; and

a redundant word line driver, responsive to a redundant word line driving signal from said redundancy control means, for driving said first and second redundant word lines.

20. The semiconductor memory device according to claim 19, wherein said redundancy control means comprises:

a master fuse latch circuit for indicating whether said first normal word line or said second normal word line has a defect and generating a master fuse signal in accordance with whether a master fuse is blown;

a fuse latch circuit for outputting a fuse latch state signal in accordance with whether a fuse is blown;

a first logic circuit for generating an address bit complementary and an address bit true when an address bit of the row address signal is supplied thereto and an inverted row address strobe signal (/RAS) is active;

a selecting circuit for selecting and outputting as an address bit signal either the address bit complementary or the address bit true in accordance with the fuse latch state signal;

a second logic circuit for generating a second word line driving signal according to the master fuse signal, the address bit signal from the selecting circuit, and at least one other address bit of the row address signal;

a third logic circuit for generating the first word line driving signal, by logically combining the second word line driving signal with other word line driving signals, each other word line driving signal corresponding to a respective bit of the row address signal; and

a fourth logic circuit for generating a redundant word line driving signal responsive to the second word line driving signal and the row address strobe signal.

21. The semiconductor memory device according to claim 16, wherein said data flip circuit comprises:

a data input buffer which receives input data in response to a data flip control signal output from said redundancy control means;

a data line sense amplifier for amplifying a potential difference between said first and second data lines; and

a data output buffer which outputs output data in response to the data flip control signal.

22. The semiconductor memory device according to claim 21, wherein said data input buffer flips and supplies the input data to said data line pair when the data flip control signal is active during a write operation, and said data output buffer flips an output of said data line sense amplifier when the data flip control signal is active during a read operation.

23. The semiconductor memory device according to claim 16, wherein said redundancy control means comprises:

a redundancy control circuit which receives a row address signal and outputs a normal word line driving signal, a redundant word line drive signal, and a data flip enable signal; and

a data flip decoder responsive to the data flip enable signal for generating a data flip control signal, and supplying the data flip control signal to said data flip circuit to control whether the data signals on said data line pair are flipped.

24. The semiconductor memory device according to claim 16, wherein said redundancy control means comprises:

a comparing circuit for comparing an input row address and a stored defective row address, the defective row address indicating which one of said first and second redundant word lines replaces said first or second normal word lines;

determining means for determining whether said first normal word line selected by the input row address is replaced with said second redundant word line or whether said second normal word line selected by the input row address is replaced with said first redundant word line,

wherein said redundancy control means outputs a redundant word line driving signal when said comparing circuit detects that the input row address and the defective row address are identical, and outputs a data flip control signal when said determining means determines that said first normal word line is replaced with said second redundant word line or when said determining means determines that said second normal word line is replaced with said first redundant word line, the data flip control signal controlling said data flip circuit to flip the data signals on said first and second data lines.

25. A semiconductor memory device with row redundancy comprising:

a plurality of first memory cells for storing true data, said first memory cells being connected to a first group of word lines;

a plurality of second memory cells for storing complementary data, said second memory cells being connected to a second group of word lines;

a first group of bit lines connected to said first and second memory cells and arranged to cross said first and second groups of word lines;

a second group of bit lines connected to said first and second memory cells and arranged to cross said first and second groups of word lines and arranged between said first group of bit lines; and

a data line pair comprising a first data line connected to said first group of bit lines and a second data line connected to said second group of bit lines;

a data flip circuit inhibited from flipping bit information on said first and second data lines when said first memory cells are connected to said first and second data lines, said data flip circuit flipping the bit information on said first and second data lines when said second memory cells are connected to said first and second data lines.

26. The semiconductor memory device according to claim 25, further comprising a decoder for generating a data flip control signal to control said data flip circuit, said data flip circuit flipping the bit information on said data line pair according to the data flip control signal.

27. The semiconductor memory device according to claim 26, wherein said data flip decoder includes a logic circuit which receives the two least significant bits of a row address of said first and second memory cells and generates the data flip control signal by determining whether the two least significant bits of the row address identify said first group or said second group of word lines.

28. The semiconductor memory device according to claim 25, wherein said first and second groups of word lines include normal and redundant word lines.

29. The semiconductor memory device according to claim 25, further comprising sense amplifiers, each connected to a corresponding one of said bit lines in said first and second groups, for amplifying a potential difference between said first and second groups of bit lines.

30. A method for testing a semiconductor memory device with row redundancy, having memory cells arranged in rows and columns, the memory cells connected to bit lines and including normal memory cells and redundant memory cells wherein the normal memory cells are connected to normal word lines and the redundant memory cells are connected to redundant word lines, said method comprising the steps of:

detecting a defective memory cell in a normal memory cell array;

inhibiting a normal word line connected to said detected defective memory cell from being accessed, and replacing said defective memory cell with a redundant memory cell connected to a redundant word line;

determining whether an input row address is identical to a stored row address, the stored address indicating the normal word line connected to said defective memory cell;

determining whether data stored in a memory cell to be accessed by the input row address is identical to data stored in a replaced normal memory cell when the input row address is identical to the stored row address;

flipping data in order to write the data in said redundant memory cell when the input row address is different from the stored row address;

reading the data written in said redundant memory cell to flip the data; and

determining whether the data written in said redundant memory cell is identical to the data read from said redundant memory cell, wherein if said data written in and read from said redundant memory cell is not identical then said redundant memory cell is defective.

31. A semiconductor memory device comprising:

a first word line connected to a first row of memory cells each of which stores data in a true data state;

a second word line connected to a second row of memory cells each of which stores data in a complementary data state;

a first bit line connected to a memory cell in said first row of memory cells;

a second bit line connected to a memory cell in said second row of memory cells; and

data flipping means for flipping data signals supplied to/from said first and second bit lines when one of said first and second word lines replaces the other of said first and second word lines.

32. The semiconductor memory device according to claim 31, further comprising:

a third word line connected to a third row of memory cells each of which stores data in the true data state; and

a fourth word line connected to a fourth row of memory cells each of which stores data in the complementary data state,

wherein said first bit line is connected to a memory cell of said third row of memory cells and said second bit line is connected to a memory cell of said fourth row of memory cells, and

wherein said data flipping means does not flip the data signals supplied to/from said first and second bit lines when one of said first and third word lines replaces the other of said first and third word lines or when one of the second and fourth word lines replaces the other of said second and fourth word lines.