Computer system and method with integrated level and edge interrupt requests at the same interrupt priority

• US 5,555,413 A
• Filed: 02/17/1995
• Issued: 09/10/1996
• Est. Priority Date: 02/17/1995
• Status: Expired due to Fees

• Current Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lohman, Terence, Perez, Roberto V., Olive, Jose A., Noll, Mark G.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/390,610
• Time in Patent Office: 571 Days
• Field of Search: 395/734, 395/736, 395/739, 395/733, 395/868
• US Class Current: 710/260
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt request signal that includes an edge transition. The second device is capable of transmitting a second interrupt request signal that comprises a level assertion. An interrupt handler is coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.

Claims

1. A computer system comprising:

a processor having an interrupt request input, the processor servicing interrupts in response to receipt of a signal at the interrupt request input;

a first device coupled to the processor, the first device capable of transmitting a first interrupt request signal that comprises an edge transition;

a second device coupled to the processor, the second device capable of transmitting a second interrupt request signal that comprises a level assertion; and

an interrupt handler coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.

2. The computer system of claim 1, wherein the interrupt handler includes an interrupt arbitrator having a first input for receiving the first interrupt request signals, a second input for receiving the second interrupt request signals, and an output for providing the first and second interrupt request signals in said sequence.

3. The computer system of claim 2, wherein the interrupt handler includes an interrupt controller having an input coupled to the output of the interrupt arbitrator, an output coupled to the interrupt request input of the processor, and an acknowledge input coupled to the processor to receive an interrupt acknowledge signal from the processor.

4. The computer system of claim 1, wherein the predetermined criteria is programmable.

5. The computer system of claim 1, wherein the predetermined criteria includes the sequence of receipt of the first and second interrupt request signals by the interrupt handler, the interrupt handler providing the first and second interrupt request signals to the processor in order of the sequence of receipt by the interrupt handler.

6. The computer system of claim 1, wherein the predetermined criteria includes whether the interrupt request signal is a first interrupt request signal comprising edge transitions or a second interrupt request signal comprising level assertions, the interrupt handler providing as an output an interrupt request signal that is a first interrupt request signal prior to an interrupt request signal that is a second interrupt request signal when both the first and second interrupt request signals are present at the interrupt handler.

7. The computer system of claim 1, wherein the predetermined criteria includes whether the interrupt request signal is a first interrupt request signal comprising edge transitions or a second interrupt request signal comprising level assertions, the interrupt handler providing as an output an interrupt request signal that is a second interrupt request signal prior to an interrupt request signal that is a first interrupt request signal when both the first and second interrupt request signals are present at the interrupt handler.

8. The computer system of claim 1, wherein the interrupt handler includes means for detecting and recording first and second interrupt request signals.

9. The computer system of claim 8, further comprising means for arbitrating among said first or second interrupt request signals to be provided as output by the interrupt handler.

10. The computer system of claim 9, further comprising means for generating in dependence on the arbitration the first or second interrupt signal as an output signal to the processor.

11. The computer system of claim 10, further comprising means for resetting the interrupt handler for receiving subsequent interrupt request signals after receiving a previous one of said interrupt request signals, and means for maintaining a record of said previous interrupt request signal.

12. The computer system of claim 1, wherein the interrupt handler includes means for converting the level assertions into edge transitions by sampling polarities of the second interrupt request signals at a completion of an end-of-interrupt command.

13. The computer system of claim 1, wherein the interrupt handler includes means for latching the first and second interrupt request signals separately and arbitrating between the first and second interrupt signals to determine the next device to seek interrupt service from the processor.

14. The computer system of claim 1, wherein the interrupt handler includes an access means for providing the first device with access to the processor, after assertion of the first interrupt request signal during a re-interruption by the second interrupt request signal, within servicing of the second interrupt request signal.

15. The computer system of claim 1, wherein the interrupt handler includes means for unconditionally preempting reinterruptions by the second device to thereby provide the first device with access to the processor.

16. An interrupt handler comprising:

a first input for receiving interrupt request signals of a first type comprising edge transitions;

a second input for receiving interrupt request signals of a second type, the second type comprising level assertions, the first type and the second type of interrupt request signals having identical priorities;

a circuit coupled to the first and second inputs and having an output, the circuit sequentially providing the interrupt request signals of the first and second type at the output according to predetermined criteria.

17. The interrupt handler of claim 16, wherein the predetermined criteria is programmable.

18. The interrupt handler of claim 16, wherein the predetermined criteria includes the sequence of receipt of the first and second type of interrupt request signals by the interrupt handler, the interrupt handler providing the first and second type of interrupt request signals to the processor in order of the sequence of receipt by the interrupt handler.

19. The interrupt handler of claim 16, wherein the predetermined criteria includes whether the interrupt request signal is a first type of interrupt request signal comprising edge transitions or a second type of interrupt request signal comprising level assertions, the interrupt handler providing as an output an interrupt request signal that is the first type of interrupt request signal prior to an interrupt request signal that is the second type of interrupt request signal when both the first and second interrupt request signals are present at the interrupt handler.

20. The interrupt handler of claim 16, wherein the predetermined criteria includes whether the interrupt request signal is the first type of interrupt request signal comprising edge transitions or the second type of interrupt request signal comprising level assertions, the interrupt handler providing as an output an interrupt request signal that is the second interrupt request signal prior to an interrupt request signal that is the first interrupt request signal when both the first and second types of interrupt request signals are present at the interrupt handler.

21. The interrupt handler of claim 16, wherein the interrupt handler includes means for detecting and recording first and second types of interrupt request signals.

22. The interrupt handler of claim 21, further comprising means for arbitrating among received interrupt request signals to be provided as output from the interrupt handler.

23. The interrupt handler of claim 22, further comprising means for generating in dependence on the arbitration the first or second type of interrupt signal as an output signal to a processor.

24. The interrupt handler of claim 23, further comprising means for resetting the interrupt handler for receiving subsequent interrupt request signals after receiving a previous one of said interrupt request signals, and means for maintaining a record of said previous interrupt request signal.

25. A method of handling interrupt requests to a processor from a plurality of sources, the method comprising the steps:

receiving in an interrupt handler a first interrupt request signal from at least one of said sources, the first interrupt request signal being an edge triggered request signal;

receiving in the interrupt handler a second interrupt request signal from at least another one of said sources, the second interrupt request signal being a level triggered request signal, the first and second interrupt request signals having identical priority;

providing as an output from the interrupt handler to a processor the first and second interrupt request signals in a sequence according to a predetermined criteria.

26. The method of claim 25, further comprising programming the interrupt handler with the predetermined criteria.

27. The method of claim 26, wherein the step of providing includes arbitrating among the received first and second interrupt request signals to be provided as output from the interrupt handler.

28. The method of claim 27, wherein the step of providing includes generating in dependence on the arbitration the first or second interrupt signal as an output signal to a processor.

29. The method of claim 28, further comprising the steps of resetting the interrupt handler for receiving subsequent interrupt request signals after receiving a previous one of said interrupt request signals, and maintaining a record of said previous interrupt request signal.

30. The method of claim 25, wherein the predetermined criteria includes the sequence of receipt of the first and second interrupt request signals by the interrupt handler, the interrupt handler providing the first and second interrupt request signals to the processor in order of the sequence of receipt by the interrupt handler.

31. The method of claim 25, wherein the predetermined criteria includes whether the interrupt request signal is an edge triggered request signal or a level triggered request signal the interrupt handler providing as an output the first interrupt request signal prior to the second interrupt request signal when both the first and second interrupt request signals are present at the interrupt handler.

32. The method of claim 25, wherein the predetermined criteria includes whether the interrupt request signal is an edge triggered request signal or a level triggered request signal, the interrupt handler providing as an output the second interrupt request signal prior to the first interrupt request signal when both the first and second interrupt request signals are present at the interrupt handler.

33. The method of claim 25, wherein the steps of receiving the first and second interrupt request signals includes means of recording the first and second interrupt request signals.