Trench capacitor cells for a dram having single monocrystalline capacitor electrode

• US 5,555,520 A
• Filed: 12/02/1994
• Issued: 09/10/1996
• Est. Priority Date: 12/03/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Koyama, Haruhiko, Kohyama, Yusuke, Sudo, Akira
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/353,368
• Time in Patent Office: 648 Days
• Field of Search: 365/149, 257/301, 257/304, 257/305, 257/306, 257/309, 257/622
• US Class Current: 365/149
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

The present structure is characterized by the electrode of a trench capacitor of a DRAM and a periphery thereof. A trench is formed adjacent to an N type region in a substrate. An insulating film is formed on the side wall of this trench and only a part of the insulating film around the upper portion of the trench is removed, forming a window. An N type polycrystalline silicon film of a lower capacitor electrode is formed over a region from the bottom of the trench to below the window, and a capacitor insulating film is formed on this polycrystalline silicon film. A polycrystalline silicon film which becomes a first upper capacitor electrode is formed on the capacitor insulating film, filling the trench up to the lower edge of the window. A monocrystalline silicon film which becomes a second upper capacitor electrode is formed on the latter polycrystalline silicon film in such a way as to contact an N type region, filling the upper portion of the trench. An insulating film similar to a gate insulating film on the substrate is formed on the monocrystalline silicon film.

Claims

1. A semiconductor memory device, comprising:

a semiconductor substrate of a first conductivity type;

a switching transistor formed on said semiconductor substrate, said switching transistor including a conductor region of a second conductivity type formed in a surface of said semiconductor substrate, and a gate insulatively spaced from a surface of said semiconductor substrate by a gate insulating film;

a trench formed adjacent to said conductor region in said semiconductor substrate;

a capacitor insulating film formed in said trench;

a capacitor electrode formed to bury said trench, at least an upper portion of said capacitor electrode in said trench being monocrystalline; and

an insulating film formed on said capacitor electrode, wherein said insulating film formed on said capacitor electrode has a same thickness as the gate insulating film of said switching transistor.

2. The semiconductor memory device according to claim 1, further comprising a semiconductor region of the first conductivity type formed in said semiconductor substrate, said semiconductor region contacting said conductor region and being doped with an impurity with a higher concentration than said semiconductor substrate.

3. The semiconductor memory device according to claim 1, further comprising:

a first semiconductor region of the first conductivity type formed in said semiconductor substrate, said first semiconductor region contacting said conductor region and the monocrystalline upper portion of said capacitor electrode and being doped with an impurity with a higher concentration than said semiconductor substrate; and

a second semiconductor region of the first conductivity type contacting said first semiconductor region and formed in the monocrystalline upper portion of said capacitor electrode.

4. A semiconductor memory device, comprising:

a semiconductor substrate of a first conductivity type;

a switching transistor formed on said semiconductor substrate, said switching transistor including a conductor region of a second conductivity type formed in a surface of said semiconductor substrate, and a gate insulatively spaced from a surface of said semiconductor substrate by a gate insulating film;

a trench formed adjacent to said conductor region in said semiconductor substrate;

a first insulating film formed on at least an upper portion of a side wall of said trench;

a capacitor insulating film formed in said trench;

a capacitor electrode formed to bury said trench, at least an upper portion of said capacitor electrode in said trench being monocrystalline;

a window formed by removing said first insulating film at one part of an upper periphery of said trench, the monocrystalline upper portion of said capacitor electrode being electrically connected to said conductor region through said window; and

a second insulating film for covering said capacitor electrode, wherein said second insulating film has a same thickness as the gate insulating film of said switching transistor.

5. The semiconductor memory device according to claim 4, wherein said conductor region extends entirely over said window and also in a depth direction near said window.

6. The semiconductor memory device according to claim 4, further comprising a semiconductor region of the first conductivity type formed in said semiconductor substrate, said semiconductor region contacting said conductor region and being doped with an impurity with a higher concentration than said semiconductor substrate.

7. The semiconductor memory device according to claim 4, further comprising:

a first semiconductor region of the first conductivity type formed in said semiconductor substrate, said first semiconductor region contacting said conductor region and the monocrystalline upper portion of said capacitor electrode and being doped with an impurity with a higher concentration than said semiconductor substrate; and

a second semiconductor region of the first conductivity type contacting said first semiconductor region and formed in the monocrystalline upper portion of said capacitor electrode.

8. A semiconductor memory device, comprising:

a semiconductor substrate of a first conductivity type;

a switching transistor formed on said semiconductor substrate, said switching transistor including a conductor region of a second conductivity type formed in a surface of said semiconductor substrate, and a gate insulatively spaced from a surface of said semiconductor substrate by a gate insulating film;

a trench formed adjacent to said conductor region in said semiconductor substrate;

a lower capacitor electrode formed in said trench and having an upper edge portion lying below said conductor region;

a first insulating film formed on at least a portion of an inner wall of said trench which extends from the upper edge portion of said lower capacitor electrode to said conductor region;

a capacitor insulating film for covering a surface of said lower capacitor electrode;

a first upper capacitor electrode portion formed in said trench and contacting said capacitor insulating film;

a monocrystalline second upper capacitor electrode portion extending to said first upper capacitor electrode to contact said conductor region and fill said trench;

a window formed by removing said first insulating film at one part of an upper periphery of said trench, the monocrystalline second upper capacitor electrode being electrically connected to said conductor region through said window; and

a second insulating film for covering said second upper capacitor electrode, wherein said second insulating film has a same thickness as the gate insulating film of said switching transistor.

9. The semiconductor memory device according to claim 8, wherein said first insulating film extends over an inner side wall of said trench excluding a bottom portion of said trench, and said lower capacitor electrode is covered over a portion from a bottom of said trench to a surface of said first insulating film.

10. The semiconductor memory device according to any one of claims 8 and 9, further comprising a semiconductor region of the first conductivity type formed in said semiconductor substrate, said semiconductor region contacting said conductor region and being doped with an impurity with a higher concentration than said semiconductor substrate.

11. The semiconductor memory device according to any one of claims 8 and 9, further comprising:

a first semiconductor region of the first conductivity type formed in said semiconductor substrate, said first semiconductor region contacting said conductor region and the monocrystalline upper portion of said capacitor electrode and being doped with an impurity with a higher concentration than said semiconductor substrate; and

a second semiconductor region of the first conductivity type contacting said first semiconductor region and formed in the monocrystalline upper portion of said capacitor electrode.

12. The semiconductor memory device according to claim 8, wherein said semiconductor substrate of the first conductivity type is a semiconductor region formed on a semiconductor substrate of the second conductivity type.

13. The semiconductor memory device according to claim 8, wherein said semiconductor substrate of the first conductivity type is a semiconductor region formed on a semiconductor substrate of the first conductivity type.

14. The semiconductor memory device according to claim 9, wherein said semiconductor substrate of the first conductivity type is a semiconductor region formed on a semiconductor substrate of the first conductivity type and further includes a semiconductor region of the second conductivity type formed in said semiconductor substrate of the first conductivity type and electrically connected to said lower capacitor electrode.

15. A semiconductor memory device, comprising:

a semiconductor substrate;

a trench formed in said semiconductor substrate;

a trench capacitor formed in said trench and including an electrode having an electrode portion of monocrystalline silicon;

a transfer transistor including source/drain regions formed on a surface of said semiconductor substrate and a control gate, constituted by a portion of a first word line, spaced from a channel region between said source/drain regions by a first insulating film portion of a first thickness; and

a second insulating film portion of a thickness equal to the thickness of said first insulating film portion for insulating said trench capacitor from a second word line, said second insulating film contacting said monocrystalline silicon electrode portion of said electrode.

16. A semiconductor memory device, comprising:

a semiconductor substrate of a first conductivity type;

a conductor region of a second conductivity type formed in a surface of said semiconductor substrate;

a trench formed adjacent to said conductor region in said semiconductor substrate;

a capacitor insulating film formed in said trench;

a capacitor electrode formed to bury said trench, at least an upper portion of said capacitor electrode in said trench being monocrystalline;

an insulating film formed on said capacitor electrode;

a first semiconductor region of the first conductivity type formed in said semiconductor substrate, said first semiconductor region contacting said conductor region and the monocrystalline upper portion of said capacitor electrode and being doped with an impurity with a higher concentration than said semiconductor substrate; and

a second semiconductor region of the first conductivity type contacting said first semiconductor region and formed in the monocrystalline upper portion of said capacitor electrode.

17. A semiconductor memory device, comprising:

a semiconductor substrate of a first conductivity type;

a conductor region of a second conductivity type formed in a surface of said semiconductor substrate;

a trench formed adjacent to said conductor region in said semiconductor substrate;

a first insulating film formed on at least an upper portion of a side wall of said trench;

a capacitor insulating film formed in said trench;

a capacitor electrode formed to bury said trench, at least an upper portion of said capacitor electrode in said trench being monocrystalline;

a window formed by removing said first insulating film at one part of an upper periphery of said trench, the monocrystalline upper portion of said capacitor electrode being electrically connected to said conductor region through said window;

a second insulating film for covering said capacitor electrode;

a first semiconductor region of the first conductivity type formed in said semiconductor substrate, said first semiconductor region contacting said conductor region and the monocrystalline upper portion of said capacitor electrode and being doped with an impurity with a higher concentration than said semiconductor substrate; and

a second semiconductor region of the first conductivity type contacting said first semiconductor region and formed in the monocrystalline upper portion of said capacitor electrode.