Method and apparatus for dielectric absorption compensation
First Claim
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1. A method for reducing dielectric absorption of a filter capapitor in a phase lock loop circuit, comprising the steps of:
- generating a negative impedance; and
sourcing current to the filter capacitor from the negative impedance when a positive transient at the filter capacitor is detected.
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Abstract
A dielectric absorption compensation circuit (300) provides an equivalent and opposite impedance to a parasitic impedance of an external capacitive load (414). The dielectric absorption compensation circuit (300) reduces lock time in a phase lock loop circuit (400) which uses an RC filter (410) including the capacitive load (414).
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Citations
16 Claims
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1. A method for reducing dielectric absorption of a filter capapitor in a phase lock loop circuit, comprising the steps of:
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generating a negative impedance; and sourcing current to the filter capacitor from the negative impedance when a positive transient at the filter capacitor is detected. - View Dependent Claims (2, 3)
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4. A dielectric absorption compensation circuit for a capacitor having a parasitic resistance and a parasitic capacitance associated therewith, comprising:
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a negative impedance circuit coupled in parallel to the capacitor for sourcing and sinking current to the capacitor, said negative impedance circuit comprising; a unity gain buffer circuit having inverting and noninverting inputs and an output, said capacitor coupled to the noninverting input; a resistive capacitive impedance substantially equivalent to the parasitic resistance and capacitance associated with the capacitor, said resistive capacitive impedance coupled to the output of the unity gain buffer circuit and to the inverting input of the unity gain buffer circuit; and a first current controlled current source coupled to the noninverting input of the unity gain buffer circuit and to the capacitor, the first current controlled current source being referenced to the resistive capacitive impedance. - View Dependent Claims (5, 6, 7)
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8. A phase lock loop circuit, comprising:
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a phase detector for receiving first and second input frequency signals and providing a phase detected signal; a low pass filter coupled to the output of the phase detector, said low pass filter including a filter capacitor having a parasitic impedance associated therewith; a dielectric absorption compensation circuit coupled in parallel to the filter capacitor and providing a substantially equivalent negative impedance to the parasitic impedance associated with the filter capacitor; a voltage controlled oscillator generating an output frequency; and a loop divider for dividing the output frequency and feeding back the divided output frequency as the second input frequency signal to the phase detector. - View Dependent Claims (9, 10, 11)
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12. A method for reducing dielectric absorption of a filter capacitor in a phase lock loop circuit, comprising the steps of:
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determining a parasitic impedance associated with the filter capacitor; generating a negative impedance which is substantially equivalent to the parasitic impedance associated with the filter capacitor; and coupling the negative impedance in parallel with said filter capacitor. - View Dependent Claims (13, 14)
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15. A method for reducing lock time of a phase lock loop circuit including a filter capacitor, comprising the steps of:
reducing the dielectric absorption associated with the filter capacitor, comprising the steps of; determining an impedance associated with the filter capacitor; generating a substantially equivalent and negative impedance to the impedance associated with the filter capacitor; coupling the substantially equivalent and negative impedance in parallel with the filter capacitor; detecting a positive transient at the filter capacitor; and sourcing current to the filter capacitor from the negative impedance when a positive transient is detected. - View Dependent Claims (16)
Specification