Low voltage flash EEPROM C-cell using fowler-nordheim tunneling

• US 5,557,569 A
• Filed: 05/25/1995
• Issued: 09/17/1996
• Est. Priority Date: 10/12/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Smayling, Michael C., Santin, Giovanni, Marotta, Giulio G., Bhat, Mousumi, D'Arrigo, Iano, Falessi, Georges
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/453,474
• Time in Patent Office: 481 Days
• Field of Search: 365/185, 365/218, 365/900, 365/63, 365/72, 257/316
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one of a plurality of Column Lines (28) at nodes (30). Each node (30) shares the programming side of two of the memory cells (24) and the non-programming side of two of the memory cells (24). The control gates of each of the memory cells (24) are connected to Word Lines (26) associated with rows of the array. To Flash Write all of the memory cells (24), the Column Lines (38) are connected to a negative medium voltage and the row lines (26) are connected to a positive medium voltage. To selectively erase one of the memory cells (24), the Column Line (28) associated with the programming side of the select memory cell transistor is connected to a positive medium voltage and the associated line (26) is connected to a positive Read voltage. The remaining Word Lines are connected to a negative Read voltage and the remaining Column Lines (28) are connected to a zero volt level.

Claims

1. An electrically programmable, non-volatile memory cell arrangement, in a semiconductor substrate, comprising:

a first doped region in said substrate of a first conductivity type, having

a central portion, and

first, second, third and fourth source/drain portions extending outwardly from said central portion;

second, third, fourth and fifth doped regions in said substrate of said first conductivity type, being disposed adjacent to and separated from, by a second conductivity type region forming a channel therebetween, said first, second, third and fourth source/drain portions, respectively;

a first floating gate structure and a second floating gate structure disposed on top of said channels formed between said first source/drain portion and said second doped region, and said second source/drain portion and said third doped region, respectively, and a first control gate structure and a second control gate structure disposed on top of said first and said second floating gate structures, respectively, forming a first storage transistor and a second storage transistor operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said second doped region and said third doped region, respectively; and

a third and a fourth floating gate structure disposed on top of said channels formed between said third source/drain portion and said fourth doped region, and said fourth source/drain portion and said fifth doped region, respectively, and third and fourth control gate structures disposed on top of said third and said fourth floating gate structures, respectively, forming a third storage transistor and a fourth storage transistor operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said third source/drain portion and said fourth source/drain portion, respectively.

2. A memory cell arrangement according to claim 1, wherein said first, second, third and fourth storage transistors are operable to be programmed by Fowler-Nordheim tunneling from only one side by having a reach-through region formed on only said one side, at which said Fowler-Nordheim tunneling occurs.

3. A memory cell arrangement according to claim 2, wherein said reach-through region comprises an extension of said third source/drain portion and said fourth source/drain portion under said third floating gate structure and said fourth floating gate structure, respectively, and further comprises an extension of said second doped region and said third doped region under said first floating gate structure and said second floating gate structure.

4. A memory cell arrangement according to claim 1, wherein said central portion of said first doped region is substantially rectangular in configuration with the source/drain regions extending from the corners thereof.

5. An electrically programmable, non-volatile memory cell array, in a semiconductor substrate, comprising a plurality of memory cell arrangements, each of said arrangements comprising:

a first doped region in said substrate of a first conductivity type, having

a central portion, and

first, second, third and fourth source/drain portions extending outwardly from said central portion;

second, third, fourth and fifth doped regions in said substrate of said first conductivity type, being disposed adjacent to and separated from, by a second conductivity type region forming a channel therebetween, said first, second, third and fourth source/drain portions, respectively;

a first and a second floating gate structure disposed on top of said channels formed between said first source/drain portion and said second doped region, and said second source/drain portion and said third doped region, respectively, and first and second control gate structures disposed on top of said first and said second floating gate structures, respectively, forming first and second storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said second doped region and said third doped region, respectively; and

a third and a fourth floating gate structure disposed on top of said channels formed between said third source/drain portion and said fourth doped region, and said fourth source/drain portion and said fifth doped region, respectively, and third and fourth control gate structures disposed on top of said third and said fourth floating gate structures, respectively, forming third and fourth storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said third source/drain portion and said fourth source/drain portion, respectively;

wherein said memory cell arrangements are arranged in an array and interconnected such that the second, third, fourth and fifth doped region of one such arrangement comprises a source/drain portion of a different one of four such arrangements adjacent to such one arrangement.

6. An electrically programmable, non-volatile memory cell arrangement, in a semiconductor substrate, for use in an array, comprising:

a first doped region in said substrate of a first conductivity type, having

a central portion,

first and second drain portions extending outwardly from said central portion, and

first and second source portions extending outwardly from said central portion;

second, third, fourth and fifth doped regions in said substrate of said first conductivity type, being disposed adjacent to and separated from, by a second conductivity type region forming a channel therebetween, said first and second drain portions and said first and second source portions, respectively;

a first and a second floating gate structure disposed on top of said channels formed between said first drain portion and said second doped region, and said second drain portion and said third doped region, respectively, and first and second control gate structures disposed on top of said first and said second floating gate structures, respectively, forming first and second storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said second doped region and said third doped region, respectively; and

a third and a fourth floating gate structure disposed on top of said channels formed between said first source portion and said fourth doped region, and said second source portion and said fifth doped region, respectively, and third and fourth control gate structures disposed on top of said third and said fourth floating gate structures, respectively, forming third and fourth storage transistors operable to be programmed by Fowler-Nordheim tunneling from only the side of said channels closest to said first source portion and said second source portion, respectively.