Frame synchronization in a performance monitoring and test system

• US 5,557,616 A
• Filed: 05/26/1995
• Issued: 09/17/1996
• Est. Priority Date: 04/02/1992
• Status: Expired due to Term

• Current Assignee: JDS Uniphase Corporation (Lumentum Holdings Inc.)
• Original Assignee: Applied Digital Access, Inc. (Lumentum Holdings Inc.)
• Inventors: Hartmann, Paul R., Cadieux, Kevin
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US08/450,494
• Time in Patent Office: 480 Days
• Field of Search: 370/100.1, 370/105.1, 370/105.2, 370/115.4, 370/108, 375/357, 375/365, 375/368
• US Class Current: 370/509
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04J 3/0623 Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04M 3/22 Arrangements for supervision, monitoring or testing
• CPC Class Codes: H04M 3/244 for multiplex systems

Abstract

A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Claims

1. A method of frame synchronization, comprising the steps of:

storing a first n bits of a digital signal into a current frame memory;

shifting n-m of the first n bits into a previous frame memory;

storing a second n bits of the digital signal into the current frame memory;

comparing at least one bit from the current memory with at least one bit from the previous memory;

incrementing a state counter when a condition of the comparison is successful; and

comparing the state counter to a threshold such that the result is indicative of frame synchronization.

2. The method of frame synchronization defined in claim 1, wherein the digital signal comprises a DS3 signal.

3. The method of frame synchronization defined in claim 1, wherein n=3.

4. The method of frame synchronization defined in claim 3, wherein m=1.

5. The method of frame synchronization defined in claim 1, wherein the current frame memory and the previous frame memory together form a shift register.

6. The method of frame synchronization defined in claim 1, wherein the shifting step occurs every 170 signal bits.

7. The method of frame synchronization defined in claim 2, wherein the maximum average reframe time is less than 1.5 milliseconds.

8. The method of frame synchronization defined in claim 2, wherein the previous frame memory comprises storage for a plurality of shifting steps and wherein the comparing step selects a bit from the previous memory which has been shifted more than one time.

9. The method of frame synchronization defined in claim 8, wherein the condition is not equal.

10. The method of frame synchronization defined in claim 8, wherein the threshold is seven.

11. A frame synchronization circuit, comprising:

a shift register comprising a current frame memory of n bits and a previous frame memory of at least n-m bits, wherein n consecutive bits of a signal containing framing bits are stored in the current frame memory and n-m bits of the current frame memory are selectively shifted into the previous frame memory, and wherein at least one potential framing bit selected from each of the current and previous frame memories is selectively shifted into a specified bit position of each of the respective frame memories; and

a first comparator for comparing at least one bit from the current memory with at least one bit from the previous memory.

12. The circuit defined in claim 11, additionally comprising:

a state counter for counting when a condition of first comparison is successful; and

a second comparator for comparing the state counter to a threshold such that the result is indicative of frame synchronization.

13. The circuit defined in claim 11, wherein the current frame memory includes a current framing bit position, representative of the current frame specified bit position, and a plurality of current adjacent framing bit positions, and wherein the previous frame memory includes a previous framing bit position and at least one previous adjacent framing bit.

14. The circuit defined in claim 11, wherein the digital signal comprises a DS3 signal.

15. The circuit defined in claim 13, wherein the previous frame memory specified bit position is delayed by one bit from the previous framing bit position.