Integrated multi-port repeater having shared resources

• US 5,557,633 A
• Filed: 02/08/1995
• Issued: 09/17/1996
• Est. Priority Date: 02/15/1990
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Staab, David, Vijeh, Nader
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): MAY, TIMOTHY
• Application Number:
  US08/385,219
• Time in Patent Office: 587 Days
• Field of Search: 375/213, 375/214, 375/224, 370/13.1, 370/14, 370/16, 379/338, 455/7, 455/9
• US Class Current: 375/213
• CPC Class Codes: G01R 29/0273 the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
• CPC Class Codes: H03K 19/018578 with at least one differential stage
• CPC Class Codes: H03K 5/023 using field effect transistors
• CPC Class Codes: H03K 5/156 Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
• CPC Class Codes: H04L 12/44 Star or tree networks
• CPC Class Codes: H04L 12/46 Interconnection of networks
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

A discrete integrated repeater device and port MAU/AUI functions shares resources among its several ports. The device includes a single multi-bit free running counter providing preselected timing intervals to a plurality of latches. A signal undergoing measurement clears the latch while a preselected timing signal sets the latch. Receipt of a timing signal at a set latch indicates success or failure of some particular condition under test. The device satisfies an IEEE 802.3 specification for execution of a link integrity test. The device is also able to selectively disable or enable the link integrity test function for particular ports. A plurality of latches, one associated with each port, is set upon carrier sense detection at the particular port. A token passing mechanism implemented with a daisy chained line coupled to each latch enables a polling of each latch to provide carrier sense information about each port in a serial format. The device shares a single PLL among all its ports by producing a logical sum of carrier sense inputs to enable activation of the PLL. A collision indication signal will override operation of the PLL to ensure data integrity and to allow the PLL to reacquire lock on its reference clock.

Claims

1. A repeater having a link integrity test disabling feature, comprising:

an integrated multiport repeater for receiving signals and for retransmitting the received signals, the multiport repeater having a plurality of ports and a control means for receiving data signals and outputting a control signal;

a link integrity test circuit coupled to a particular one of the plurality of ports for implementing a link integrity test for the particular one port; and

linktest control means, coupled to the link integrity test circuit and to the control means, for disabling the link integrity test circuit for the particular one port in response to the control signal when the particular one port is connected to a node that does not generate linkbeats.

2. A repeater, comprising:

an integrated multiport repeater for receiving signals and for retransmitting the received signals, the multiport repeater having a plurality of ports and a control means for receiving data signals and outputting a first control signal;

a link integrity test circuit coupled to a particular one of the plurality of ports for implementing a link integrity test for the particular one port and for disabling the particular port for nonreceipt of a plurality of linktest pulses;

linktest control means, coupled to the link integrity test circuit and responsive to a second control signal, for inhibiting the disablement of the particular port by the link integrity test circuit for nonreceipt of a plurality of linktest pulses; and

a memory associated with the particular one port and coupled to the control means and responsive to the first control signal for outputting the second control signal in response to the output of the first control signal.

3. The repeater of claim 2 wherein each of a plurality of memories are coupled to one of the plurality of ports.

4. The repeater of claim 3 wherein each of the plurality of memories respond separately to control information to individually disable the link integrity test for each one of the plurality of ports when each one of the plurality of parts are connected to a node that does not generate linkbeats.

5. The repeater of claim 2 wherein the memory is further responsive to the data signals to deassert the first control signal and thereby reenable linktest reception for the particular one port when the particular port requires linkbeat reception.

6. A method of disabling a link integrity test function on a port of a multiport repeater while maintaining participation of the port on a network, comprising the steps of:

receiving control information at a circuit, the circuit including a port and a linktest control circuit coupled to the port for controlling the reception of a linktest pulse;

if the control information indicates the reception of the linktest pulse for the port is to be disabled, outputting a first control signal from a memory associated with the port and coupled to the linktest control circuit; and

outputting a second control signal to the port from the linktest control circuit if the port is to be disabled from receiving the linktest pulse.