Caching FIFO and method therefor

• US 5,557,733 A
• Filed: 04/02/1993
• Issued: 09/17/1996
• Est. Priority Date: 04/02/1993
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Hicok, Gary D., Lehman, Judson A.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/042,306
• Time in Patent Office: 1,264 Days
• Field of Search: 345/114, 345/119, 345/152, 345/172, 345/173, 345/182, 345/189, 345/190, 345/200, 365/189.03, 365/189.04, 365/189.05, 365/201, 365/230.05, 395/100, 395/129, 395/131, 395/132, 395/143, 395/157, 395/162, 395/164, 395/166, 395/163, 395/250, 395/275, 395/500, 395/325, 395/425, 395/700, 395/800
• US Class Current: 345/554
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Abstract

A memory subsystem for use between a CPU and a graphics controller in a typical small computer system has a cache interface for the CPU and a FIFO interface for the graphics controller. This configuration optimizes the data transfers for both the CPU and the graphics controller, and allows both to operate in a manner generally asynchronous to each other. This caching FIFO provides enhanced performance by matching the interface to the unique data requirements of the devices accessing the data within the caching FIFO. For the CPU, the caching FIFO appears as a normal data cache. For the graphics controller, the caching FIFO appears as a normal dual port FIFO, which optimizes the highly sequential data transfers characteristic of graphics controllers. The simple design of the caching FIFO provides maximum performance for a minimum of gates, making the circuit well-suited to efficient implementation in silicon.

Claims

1. A memory subsystem for transferring data between a CPU and a graphics controller in a small computer system comprising, in combination:

Random Access Memory (RAM) means for storing said data;

first interface means coupled to said CPU and to said RAM means for providing a cache interface for transferring said data from said CPU to said RAM means and from said RAM means to said CPU; and

second interface means coupled to said graphics controller and to said RAM means for providing a dual port First-In-First-Out (FIFO) interface for transferring said data from said graphics controller to said RAM means and from said RAM means to said graphics controller.

2. The memory subsystem of claim 1 wherein said RAM means comprising a three port RAM having a first port dedicated to reading said data from said RAM means by said CPU, having a second port dedicated to reading said data from said RAM means by said graphics controller, and having a third port dedicated to writing said data from said CPU and from said graphics controller into said RAM means.

3. The memory subsystem of claim 1 wherein said cache interface and said dual port FIFO interface together comprising:

cache logic means for controlling flow of said data during a CPU read from said RAM means and during a CPU write to said RAM means;

FIFO logic means for controlling flow of said data during a graphics controller read from said RAM means and during a graphics controller write to said RAM means;

latch means for storing said data during said graphics controller write to said RAM means; and

multiplexer means for routing said data appropriately during said graphics controller write to said RAM means, during said CPU write to said RAM means, and during said CPU read from said RAM means.

4. A memory subsystem for transferring data between a CPU and a graphics controller in a small computer system comprising, in combination:

Random Access Memory (RAM) means for storing said data, comprising a three port RAM having a first port dedicated to reading said data from said RAM means by said CPU, having a second port dedicated to reading said data from said RAM means by said graphics controller, and having a third port dedicated to writing said data from said CPU and from said graphics controller into said RAM means;

first interface means coupled to said CPU and to said RAM means for providing a cache interface for transferring said data from said CPU to said RAM means and from said RAM means to said CPU; and

second interface means coupled to said graphics controller and to said RAM means for providing a dual port First-In-First-Out (FIFO) interface for transferring said data from said graphics controller to said RAM means and from said RAM means to said graphics controller;

said cache interface and said dual port FIFO interface together comprising;

cache logic means for controlling flow of said data during a CPU read from said RAM means and during a CPU write to said RAM means;

FIFO logic means for controlling flow of said data during a graphics controller read from said RAM means and during a graphics controller write to said RAM means;

latch means for storing said data during said graphics controller write to said RAM means; and

multiplexer means for routing said data appropriately during said graphics controller write to said RAM means, during said CPU write to said RAM means, and during said CPU read from said RAM means.

5. A method for transferring data between a CPU and a graphics controller in a small computer system including the steps of:

providing Random Access Memory (RAM) means for storing said data;

providing a cache interface for transferring said data from said CPU to said RAM means and from said RAM means to said CPU;

providing a dual port First-In-First-Out (FIFO) interface for transferring said data from said graphics controller to said RAM means and from said RAM means to said graphics controller;

transferring said data from said CPU to said RAM means through said cache interface;

transferring said data from said RAM means to said CPU through said cache interface;

transferring said data from said graphics controller to said RAM means through said dual port FIFO interface;

transferring said data from said RAM means to said graphics controller through said dual port FIFO interface;

said data transferring to and from said RAM means from said CPU and said data transferring to and from said RAM means from said graphics controller occurring substantially asynchronously to each other.

6. The method of claim 5 wherein said RAM means comprising a three port RAM having a first port dedicated to reading said data from said RAM means by said CPU, having a second port dedicated to reading said data from said RAM means by said graphics controller, and having a third port dedicated to writing said data from said CPU and from said graphics controller into said RAM means.

7. The method of claim 5 wherein said cache interface and said dual port FIFO interface together comprising:

cache logic means for controlling flow of said data during a CPU read from said RAM means and during a CPU write to said RAM means;

FIFO logic means for controlling flow of said data during a graphics controller read from said RAM means and during a graphics controller write to said RAM means;

latch means for storing said data during said graphics controller write to said RAM means; and

multiplexer means for routing said data appropriately during said graphics controller write to said RAM means, during said CPU write to said RAM means, and during said CPU read from said RAM means.