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Cache burst architecture for parallel processing, such as for image processing

  • US 5,557,734 A
  • Filed: 06/17/1994
  • Issued: 09/17/1996
  • Est. Priority Date: 06/17/1994
  • Status: Expired due to Fees
First Claim
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1. In a processing system for performing processing operations in parallel upon a data matrix stored in a memory means having L rows and M columns, where L and M are integers greater than one, the system including M processing units wherein each of the M processing units is associated with a respective column of the memory means, a method of transferring data between the memory means and the processing units, comprising the step of:

  • (A) shifting, in a first clock cycle, each bit of a first row of M data bits from the memory means one or more column positions to the processing unit associated with respectively adjacent columns of the memory means.

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