Test apparatus and method for a computer parallel port

• US 5,557,741 A
• Filed: 04/28/1994
• Issued: 09/17/1996
• Est. Priority Date: 04/28/1994
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Jones, Jerry M.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Decady, Albert
• Application Number:
  US08/234,447
• Time in Patent Office: 873 Days
• Field of Search: 371/15.1, 371/20.1, 371/20.4, 371/20.5, 371/20.6, 371/24, 371/27, 371/67.1, 371/68.1, 371/68.3, 371/68.2, 370/13, 370/15, 395/183.01, 395/183.06, 395/183.19
• US Class Current: 714/43
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units

Abstract

A test apparatus and method for testing a port of a computer system. The port has a plurality of output lines and a single input line. The apparatus includes: (1) a receiver circuit for receiving a datum transmitted in parallel from the computer system via the plurality of output lines, (2) a storage circuit, coupled to the receiver circuit, for temporarily storing the datum from the output lines and (3) a transmitter circuit, coupled to the storage circuit, for serially transmitting the datum via the input line to the computer system. The computer system compares the datum transmitted from the computer system to the datum received by the computer system to verify a proper functioning of the output lines and input line.

Claims

1. A System for testing a port of a computer, said port having a plurality of output lines and an input line, said system including a test apparatus comprising:

means for coupling said test apparatus to said output lines of said computer port;

means for receiving a datum transmitted in parallel from said computer via said plurality of output lines;

means, coupled to said receiving means, for temporarily storing said datum from said output lines;

means, coupled to said storing means, for serially transmitting said datum via said input line to said computer;

said system further comprising means, within said computer, for comparing said datum transmitted from said computer to said datum received by said computer to verify a proper functioning of said output lines and input line.

2. The system as recited in claim 1 wherein said coupling means includes means for coupling electrical power from said computer to said test apparatus.

3. The system as recited in claim 1 wherein said port further has a plurality of output control lines and a corresponding plurality of input control lines, said apparatus further comprising a loopback circuit for coupling ones of said plurality of output control lines to corresponding ones of said input control lines, said computer system comparing signals transmitted from said computer system via said plurality of output control lines to signals received by said computer system via said plurality of corresponding input control lines to verify a proper functioning of said output and input control lines.

4. The system as recited in claim 1 wherein said port is a unidirectional port.

5. The system as recited in claim 1 wherein said port is a bidirectional port and said transmitter circuit is adapted to transmit said datum in parallel to said computer system via said plurality of output lines.

6. The system as recited in claim 1 further comprising a diagnostic routine executing in said computer system for causing said computer system to transmit said datum to said apparatus, causing said computer system to receive said datum from said apparatus and comparing said datum transmitted from said computer system to said datum received by said computer system to verify said proper functioning of said output lines and input line.

7. The system as recited in claim 1 wherein said input line is an error line.

8. The system as recited in claim 1 further comprising:

a port connector containing pins corresponding to said plurality of output lines and said input line; and

a backshell coupled to said port connector and completely containing said receiver, storage and transmitter circuits.

9. The system as recited in claim 1 wherein said receiver, storage and transmitter circuits are embodied in a tri-state shift register.

10. The system as recited in claim 1 wherein said computer system is a personal computer (PC) and said port is a parallel port.

11. A method for testing a port of a computer system, said port having a plurality of output lines and a single input line, comprising the steps of:

connecting said port of said computer to a test apparatus;

receiving a datum transmitted in parallel from said computer via said plurality of output lines into a receiver circuit of said test apparatus;

temporarily storing said datum from said output lines in a storage circuit of said test apparatus, said storage circuit being coupled to said receiver circuit;

serially transmitting said datum via said input line to said computer by means of a transmitter circuit of said test apparatus, said transmitter circuit being coupled to said storage circuit; and

comparing, within said computer, said datum transmitted from said computer to said datum received by said computer to verify a proper functioning of said output lines and input line.

12. The method as recited in claim 11 further comprising the step of providing power to said storage circuit from said computer power supply.

13. The method as recited in claim 11 further comprising the steps of:

coupling ones of a plurality of output control lines to corresponding ones of a plurality of input control lines with a loopback circuit; and

comparing signals transmitted from said computer system via said plurality of output control lines to signals received by said computer system via said plurality of corresponding input control lines to verify a proper functioning of said output and input control lines.

14. The method as recited in claim 11 wherein said port is a unidirectional port.

15. The method as recited in claim 11 further comprising the step of executing a diagnostic routine in said computer system, said diagnostic routine causing said computer system to transmit said datum to said apparatus, causing said computer system to receive said datum from said apparatus and comparing said datum transmitted from said computer system to said datum received by said computer system to verify said proper functioning of said output lines and input line.

16. The method as recited in claim 11 wherein said input line is an error line.

17. The method as recited in claim 11 further comprising:

providing a port connector containing pins corresponding to said plurality of output lines and said input line; and

completely containing said receiver, storage and transmitter circuits in a backshell coupled to said port connector.

18. The method as recited in claim 11 comprising the step of embodying said receiver, storage and transmitter circuits in a tri-state shift register.

19. The method as recited in claim 11 wherein said computer system is a personal computer (PC) and said port is a parallel port.

20. The method as recited in claim 11 wherein said port is a bi-directional port, said method further comprising the steps of:

identifying said port as a bi-directional port; and

transmitting said datum in parallel to said computer via said plurality of output lines with said transmitter circuit in response to said identification.

21. A test apparatus for testing a port of a computer system, said port having a plurality of output lines and a single input line, a diagnostic routine executing in said computer system, comprising:

a receiver circuit for receiving a datum transmitted in parallel from said computer system via said plurality of output lines;

a storage circuit, coupled to said receiver circuit, for temporarily storing said datum from said output lines, said computer system providing power to said storage circuit;

a transmitter circuit, coupled to said storage circuit, for serially transmitting said datum via said input line to said computer system, said diagnostic routine causing said computer system to transmit said datum to said apparatus and causing said computer system to receive said datum from said apparatus, said diagnostic routine comparing said datum transmitted from said computer system to said datum received by said computer system to verify a proper functioning of said output lines and input line;

a port connector containing pins corresponding to said plurality of output lines and said input line; and

a backshell coupled to said port connector and completely containing said receiver, storage and transmitter circuits.

22. The apparatus as recited in claim 21 wherein said port further has a plurality of output control lines and a corresponding plurality of input control lines, said apparatus further comprising a loopback circuit for coupling ones of said plurality of output control lines to corresponding ones of said input control lines, said computer system comparing signals transmitted from said computer system via said plurality of output control lines to signals received by said computer system via said plurality of corresponding input control lines to verify a proper functioning of said output and input control lines.

23. The apparatus as recited in claim 21 wherein said port is a unidirectional port.

24. The apparatus as recited in claim 21 wherein said port is a bidirectional port and said transmitter circuit is adapted to transmit said datum in parallel to said computer system via said plurality of output lines.

25. The apparatus as recited in claim 21 wherein said input line is an error line.

26. The apparatus as recited in claim 21 wherein said receiver, storage and transmitter circuits are embodied in a tri-state shift register.

27. The apparatus as recited in claim 21 wherein said computer system is a personal computer (PC) and said port is a parallel port.

28. The apparatus as recited in claim 21 wherein said port comprises a plurality of output control lines for allowing said diagnostic routine to control said apparatus.

29. The apparatus as recited in claim 21 wherein said storage circuit is a latch in a tri-state shift register.

30. The apparatus as recited in claim 21 wherein said apparatus has 8 output lines.

31. A method of testing a port of a computer system, said port having a plurality of output lines and a single input line, comprising the steps of:

coupling a port connector of a test apparatus to a corresponding port connector of said port, said test apparatus port connector containing pins corresponding to said plurality of output lines and said input line, a backshell coupled to said test apparatus port connector completely containing said apparatus;

executing a diagnostic routine in said computer system;

receiving a datum transmitted in parallel from said computer system via said plurality of output lines into a receiver circuit of said apparatus;

temporarily storing said datum from said output lines in a storage circuit of said apparatus, said storage circuit coupled to said receiver circuit, said computer system providing power to said storage circuit;

serially transmitting said datum via said input line to said computer system with a transmitter circuit of said apparatus, said transmitter circuit coupled to said storage circuit, said diagnostic routine causing said computer system to transmit said datum to said apparatus and causing said computer system to receive said datum from said apparatus; and

comparing said datum transmitted from said computer system to said datum received by said computer system with said diagnostic routine to verify a proper functioning of said output lines and input line.

32. The method as recited in claim 31 further comprising the steps of:

coupling ones of a plurality of output control lines to corresponding ones of a plurality of input control lines with a loopback circuit; and

comparing signals transmitted from said computer system via said plurality of output control lines to signals received by said computer system via said plurality of corresponding input control lines to verify a proper functioning of said output and input control lines.

33. The method as recited in claim 31 wherein said port is a unidirectional port.

34. The method as recited in claim 31 wherein said port is a bidirectional port, said method further comprising the step of transmitting said datum in parallel to said computer system via said plurality of output lines with said transmitter circuit.

35. The method as recited in claim 31 wherein said input line is an error line.

36. The method as recited in claim 31 comprising the step of embodying said receiver, storage and transmitter circuits in a tri-state shift register.

37. The method as recited in claim 31 wherein said computer system is a personal computer (PC) and said port is a parallel port.

38. The method as recited in claim 31 wherein said step of executing comprises the step of controlling said apparatus with a plurality of output control lines.

39. The method as recited in claim 31 wherein said step of receiving comprises the step of receiving a datum transmitted in parallel from said computer system via said plurality of output lines into a latch in a tri-state shift register.

40. The method as recited in claim 31 wherein said apparatus has 8 output lines.

41. A test apparatus for testing a parallel port of a personal computer (PC), said port having 8 data output lines and a single error input line, a diagnostic routine executing in said computer system, comprising:

a receiver circuit for receiving a datum transmitted in parallel from said computer system via said plurality of data output lines;

a storage circuit, coupled to said receiver circuit, for temporarily storing said datum from said data output lines, said computer system providing power to said storage circuit;

a transmitter circuit, coupled to said storage circuit, for serially transmitting said datum via said error input line to said computer system, said diagnostic routine causing said computer system to transmit said datum to said apparatus and causing said computer system to receive said datum from said apparatus, said diagnostic routine comparing said datum transmitted from said computer system to said datum received by said computer system to verify a proper functioning of said data output lines and error input line;

a plurality of output control lines and a corresponding plurality of input control lines, some of said plurality of output control lines allowing said diagnostic routine to control said apparatus;

a loopback circuit for coupling ones of said plurality of output control lines to corresponding ones of said input control lines, said computer system comparing signals transmitted from said computer system via said plurality of output control lines to signals received by said computer system via said plurality of corresponding input control lines to verify a proper functioning of said output and input control lines;

a port connector containing pins corresponding to said plurality of data output lines, said error input line, said output control lines and said input control lines; and

a backshell coupled to said port connector and completely containing a tri-state shift register embodying said receiver, storage and transmitter circuits.

42. The apparatus as recited in claim 41 wherein said port is a unidirectional port.

43. The apparatus as recited in claim 41 wherein said port is a bidirectional port and said transmitter circuit is adapted to transmit said datum in parallel to said computer system via said plurality of data output lines.

44. A method of testing a parallel port of a personal computer (PC), said port having 8 data output lines and a single error input line, comprising the steps of:

coupling a port connector of a test apparatus to a corresponding port connector of said port, said test apparatus port connector containing pins corresponding to said plurality of data output lines and said error input line, a backshell coupled to said test apparatus port connector completely containing a tri-state shift register embodying said apparatus;

coupling ones of a plurality of output control lines to corresponding ones of a plurality of input control lines with a loopback circuit in said apparatus, some of said plurality of output control lines controlling said apparatus;

executing a diagnostic routine in said computer system;

receiving a datum transmitted in parallel from said computer system via said plurality of data output lines into a receiver circuit of said apparatus;

temporarily storing said datum from said data output lines in a storage circuit of said apparatus, said storage circuit coupled to said receiver circuit, said computer system providing power to said storage circuit;

comparing signals transmitted from said computer system via said plurality of output control lines to signals received by said computer system via said plurality of corresponding input control lines to verify a proper functioning of said output and input control lines;

serially transmitting said datum via said error input line to said computer system with a transmitter circuit of said apparatus, said transmitter circuit coupled to said storage circuit, said diagnostic routine causing said computer system to transmit said datum to said apparatus and causing said computer system to receive said datum from said apparatus; and

comparing said datum transmitted from said computer system to said datum received by said computer system with said diagnostic routine to verify a proper functioning of said data output lines and error input line.

45. The method as recited in claim 44 wherein said port is a unidirectional port.

46. The method as recited in claim 44 wherein said port is a bidirectional port, said method further comprising the step of transmitting said datum in parallel to said computer system via said plurality of data output lines with said transmitter circuit.