ESD protection improvement

• US 5,559,352 A
• Filed: 12/12/1994
• Issued: 09/24/1996
• Est. Priority Date: 10/22/1993
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsue, Chen-Chiu, Ko, Joe
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/354,373
• Time in Patent Office: 652 Days
• Field of Search: 257/173, 257/174, 257/328, 257/344, 257/355, 257/408, 257/546
• US Class Current: 257/328
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

A method of forming an ESD protection device with reduced breakdown voltage, simultaneously with an integrated circuit which includes FET devices, and the resultant device structure, are described. A silicon substrate is provided on which there are field oxide regions, gates, and active regions. A first ion implant of a conductivity-imparting dopant is performed in a vertical direction into the active regions of the ESD protection device and the FET devices. A first insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The first insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. A second ion implant of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant is performed into active regions of both the ESD protection device and the FET devices. A second insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The second insulating layer is patterned to form contact openings to the active regions. Finally, a third ion implant of a conductivity-imparting dopant, with opposite conductivity from the first and second ion implants, having equal concentration to dopant from the first ion implant, is performed through the contact openings into active regions of the ESD protection device.

Claims

1. An ESD protection device with reduced junction breakdown voltage, connected to an integrated circuit which includes FET devices, comprising:

a silicon substrate having a first conductivity type;

field oxide regions in and on said silicon substrate for isolation of said ESD protection device;

a gate with adjacent spacers for said ESD protection device, between said field oxide regions;

source/drain regions for said ESD protection device between said gate and said field oxide regions, with each source/drain region comprising;

a first lightly implanted region having a second conductivity type opposite to said first conductivity type, under one of said spacers;

a heavier implanted region of the same conductivity type as said first lightly implanted region, located between said first lightly implanted region and one of said field oxide regions;

a second lightly implanted region of same conductivity type as said silicon substrate, centered under said heavier implanted region.

2. The ESD protection device of claim 1 wherein said first conductivity type is P-type, and said second conductivity type is N-type.

3. The ESD protection device of claim 2 wherein said P-type conductivity caused by implanted ions of boron.

4. The ESD protection device of claim 2 wherein said N-type conductivity caused by implanted ions of phosphorus.

5. The ESD protection device of claim 1 wherein said first conductivity type is N-type, and said second conductivity type is P-type.

6. The ESD protection device of claim 5 wherein said P-type conductivity is caused by implanted ions of boron.

7. The ESD protection device of claim 6 wherein said N-type conductivity is caused by implanted ions of phosphorus.

8. An ESD protection circuit, having first and second ESD protection devices, connected to an integrated circuit which includes FET devices, and connected to an input/output pad, comprising:

a silicon substrate having a first conductivity type;

field oxide regions in and on said silicon substrate for isolation of said ESD protection devices;

gates with adjacent spacers for each of said ESD protection devices, between said field oxide regions;

source/drain regions for said ESD protection devices between said gates and said field oxide regions, with each source/drain region comprising;

a first lightly implanted region having a second conductivity type opposite to said first conductivity type, under one of said spacers;

a heavier implanted region of the same conductivity type as said first lightly implanted region, located between said first lightly implanted region and one of said field oxide regions;

a second lightly implanted region of same conductivity type as said silicon substrate, centered under said heavier implanted region;

a first electrical connection between said input/output pad, said drain regions of said first and second ESD protection devices, and said integrated circuit;

a second electrical connection to ground of said gates of said first and second ESD protection devices, and said source region of said second ESD protection device; and

a third electrical connection, to a voltage source, of said source of said first ESD protection device.