Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
First Claim
1. A dynamic threshold insulated gate field effect device comprisinga first transistor formed in a first semiconductor body region and having a source, a drain, a channel region between said source and said drain, and a gate contact overlying said channel region,a second transistor formed in a second semiconductor body region and having a source, a drain, a channel region between said source and said drain, and a gate contact overlying said channel region,means for interconnecting said drain of said second transistor to said gate of said first transistor,means for interconnecting said source of said second transistor to said first semiconductor body region,means for interconnecting said source of said first transistor to a reference potential, andmeans for biasing said gate contact of said second transistor with an appropriate gate voltage whereby said second transistor applies a forward bias to said first semiconductor body region relative to said source of said first transistor.
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Accused Products
Abstract
A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.
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Citations
2 Claims
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1. A dynamic threshold insulated gate field effect device comprising
a first transistor formed in a first semiconductor body region and having a source, a drain, a channel region between said source and said drain, and a gate contact overlying said channel region, a second transistor formed in a second semiconductor body region and having a source, a drain, a channel region between said source and said drain, and a gate contact overlying said channel region, means for interconnecting said drain of said second transistor to said gate of said first transistor, means for interconnecting said source of said second transistor to said first semiconductor body region, means for interconnecting said source of said first transistor to a reference potential, and means for biasing said gate contact of said second transistor with an appropriate gate voltage whereby said second transistor applies a forward bias to said first semiconductor body region relative to said source of said first transistor.
Specification