System and method for model-based verification of local design rules
First Claim
1. A system for model-based verification of local design rules in a physical integrated circuit design, the system comprising:
- a processing unit having an input and an output, for performing the model-based local design rule verification of the physical integrated circuit design according to a sequence of program instruction steps;
a verification database having an input and an output, for storing a cell reference graph representing the physical integrated circuit design as a set of cells, each cell representing one of a constituent model and a shape model on a physical mask design, each constituent model comprising a reference to one of a shape model and a reference to a second cell at a lower hierarchical level, the output of the verification database coupled to the input of the processing unit, the input of the verification database coupled to the output of the processing unit, said verification database further comprising;
a reference graph register having an input and an output, for storing the cell reference graph representation of the physical integrated circuit design, the output of the reference graph register coupled to the input of the processing unit, the input of the reference graph register coupled to the output of the processing unit;
a results register having an input and an output, for storing a verification result, the input of the results register coupled to the output of the processing unit, and the output of the results register coupled to the input of the processing unit;
said processing unit overriding one of said verification results and said results register storing a new verification result associated with a first cell of said set of cells if a position of one of a second cell of said set of cells and a shape model violates said verification function; and
a verification memory having an input and an output, for storing said verification function and one or more models during model-based local design rule verification, the output of the verification memory coupled to the input of the processing unit.
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Abstract
A system for model-based verification of local design rules comprises a processing unit, a verification database wherein a cell reference graph representing an integrated circuit design as a hierarchical collection of cells is stored, a verification function memory wherein a verification function is stored, a friendly worklayer memory, and an unfriendly worklayer memory. Each cell can include shape models and references to lower-level cells. The processing unit first verifies each cell in the cell reference graph that does not reference any lower-level cells, after which the processing unit verifies each cell for which all lower-level cells referenced have been previously verified. During the verification of a selected cell, the processing unit determines whether models in the selected cell interact with other models in the selected cell or with any lower-level cell. Interacting models are referred to as being "unfriendly," and non-interacting models are referred to as being "friendly." The processing unit references a previously calculated verification result when models are friendly, and applies a verification function to models that are unfriendly.
A method for model-based verification of local design rules comprises the steps of: selecting a cell for verification; selecting a verification function; determining whether models in the cell reference graph are unfriendly with a model in the selected cell; applying the selected verification function to each model involved in an unfriendly interaction; and generating an override in the event that a previously calculated verification result is invalid due to unfriendliness between models.
68 Citations
23 Claims
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1. A system for model-based verification of local design rules in a physical integrated circuit design, the system comprising:
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a processing unit having an input and an output, for performing the model-based local design rule verification of the physical integrated circuit design according to a sequence of program instruction steps; a verification database having an input and an output, for storing a cell reference graph representing the physical integrated circuit design as a set of cells, each cell representing one of a constituent model and a shape model on a physical mask design, each constituent model comprising a reference to one of a shape model and a reference to a second cell at a lower hierarchical level, the output of the verification database coupled to the input of the processing unit, the input of the verification database coupled to the output of the processing unit, said verification database further comprising; a reference graph register having an input and an output, for storing the cell reference graph representation of the physical integrated circuit design, the output of the reference graph register coupled to the input of the processing unit, the input of the reference graph register coupled to the output of the processing unit; a results register having an input and an output, for storing a verification result, the input of the results register coupled to the output of the processing unit, and the output of the results register coupled to the input of the processing unit;
said processing unit overriding one of said verification results and said results register storing a new verification result associated with a first cell of said set of cells if a position of one of a second cell of said set of cells and a shape model violates said verification function; anda verification memory having an input and an output, for storing said verification function and one or more models during model-based local design rule verification, the output of the verification memory coupled to the input of the processing unit. - View Dependent Claims (2, 3, 4, 5, 22, 23)
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6. In a system having a processing unit, a verification memory storing a verification function, and a verification database storing a cell reference graph representing a physical integrated circuit design as a hierarchical collection of cells, each cell in the cell reference graph associated with a hierarchical level and comprising one of a reference to a constituent model and a reference to a shape model, each constituent model comprising one from the group of a reference to a shape model and a reference to another cell at a lower hierarchical level, a method for model-based verification of local design rules in the physical integrated circuit design comprising the steps of:
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selecting a cell for verification; selecting a verification function; identifying each shape model referenced by the selected cell that is unfriendly with another shape model referenced by the selected cell; determining whether the selected cell references a first cell at a lower hierarchical level that is unfriendly with one of said selected cell shape models and a second cell at one of the same hierarchical level or a lower hierarchical level as said first cell; performing a decomposition upon the first cell and the second cell if the selected cell references a first cell at a lower hierarchical level that is unfriendly with a second cell at one of the same hierarchical level and said lower hierarchical level as the first cell; applying said selected verification function to the identified unfriendly shape models to determine a verification result representative of whether a design rule associated with said selected verification function is violated; and storing said verification result in a memory location associated with said selected cell and overriding any previous verification result associated with one of said first cell and said second cell, in said verification memory. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification