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Display controller incorporating cache memory dedicated for VRAM

  • US 5,559,952 A
  • Filed: 03/22/1994
  • Issued: 09/24/1996
  • Est. Priority Date: 03/23/1993
  • Status: Expired due to Fees
First Claim
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1. A display control system comprising:

  • an image memory for storing image data generated by a CPU of a host computer including said display control system and a drawing processor arranged in said display control system;

    display means for displaying the image data, stored in said image memory, on a display;

    a cache memory, including first and second cache memory blocks from/in which data can be independently read/written, for storing part of the image data stored in said image memory, said cache memory being designed such that the image data is read/written therefrom/therein in accordance with a read/write request from said CPU of said host computer or said drawing processor;

    memory control means;

    cache switching means for alternately switching and connecting said first and second cache memory blocks to the processor and said memory control means so as to allow the processor and said memory control means to simultaneously execute cache access; and

    hit detection means for detecting a cache hit/cache miss depending on whether data, read access of which is requested by said CPU of the host computer or said drawing processor, is stored in said cache memory;

    said memory control means being connected to said cache memory, said image memory, and said hit detection means for replacing contents of said cache memory by transferring image data stored in said image memory to said cache memory in response to a cache miss detected by said hit detection means.

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