Display controller incorporating cache memory dedicated for VRAM

• US 5,559,952 A
• Filed: 03/22/1994
• Issued: 09/24/1996
• Est. Priority Date: 03/23/1993
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujimoto, Akihisa
• Primary Examiner(s): Bayerl, Raymond J.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/215,948
• Time in Patent Office: 917 Days
• Field of Search: 395/162-166, 395/250, 395/275, 395/400, 395/425, 345/185, 345/186, 345/189, 345/190, 345/201, 364/243, 364/243.41, 364/243.44, 364/243.45, 364/246.11, 364/246.3
• US Class Current: 345/557
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A frame buffer cache is arranged to store part of image data in an image memory so that a CPU and a drawing processor can perform image data read/write operations by only accessing the frame buffer cache. Therefore, the image data read/write operations of the CPU and the drawing processor can be performed simultaneously with the access to a dual port image memory, thus improving the drawing performance of the CPU and the drawing processor.

Claims

1. A display control system comprising:

an image memory for storing image data generated by a CPU of a host computer including said display control system and a drawing processor arranged in said display control system;

display means for displaying the image data, stored in said image memory, on a display;

a cache memory, including first and second cache memory blocks from/in which data can be independently read/written, for storing part of the image data stored in said image memory, said cache memory being designed such that the image data is read/written therefrom/therein in accordance with a read/write request from said CPU of said host computer or said drawing processor;

memory control means;

cache switching means for alternately switching and connecting said first and second cache memory blocks to the processor and said memory control means so as to allow the processor and said memory control means to simultaneously execute cache access; and

hit detection means for detecting a cache hit/cache miss depending on whether data, read access of which is requested by said CPU of the host computer or said drawing processor, is stored in said cache memory;

said memory control means being connected to said cache memory, said image memory, and said hit detection means for replacing contents of said cache memory by transferring image data stored in said image memory to said cache memory in response to a cache miss detected by said hit detection means.

2. A system according to claim 1, wherein said memory control means comprises prefetch means for reading out image data, succeeding image data stored in one of said first and second cache memory blocks which is connected to the processor, from said image memory, and prefetching the readout image data to the other of said first and second cache memory blocks.

3. A system according to claim 2, wherein said prefetch means read-accesses said image memory in the page mode and continuously transfers a plurality of continuous image data from said image memory to said cache memory in an order of addresses.

4. A system according to claim 2, further comprising hit detection means for detecting a cache hit/cache miss depending on whether data, read access of which is requested by the processor, is stored in said cache memory block connected to the processor, and

wherein in response to said cache miss detected by said hit detection means, said cache switching means switches said cache memory block connected to the processor to said cache memory block, to which the image data is prefetched by said prefetch means.

5. A system according to claim 1, further comprising hit detection means for detecting a cache hit/cache miss depending on whether data, write access of which is requested by the processor, is data on a predetermined row line of said image memory, and

wherein in response to a cache miss detected by said hit detection means, said cache switching means switches said cache memory block to which the process is connected, from one of said first and second cache memory blocks to the other.

6. A system according to claim 5, wherein said memory control means writes image data, stored in said cache memory block newly connected to said memory control means, in said image memory in response to connection switching of a write cache memory block by said cache switching means.

7. A display control system comprising:

an image memory for storing image data generated by a CPU of a host computer including said display control system and a drawing processor arranged in said display control system;

display means for displaying the image data, stored in said image memory, on a display;

a cache memory for storing part of the image data stored in said image memory, said cache memory being designed such that the image data is read/written therefrom/therein in accordance with a read/write request from said CPU of said host computer or said drawing processor, said cache memory including first and second write cache memory blocks for respectively storing image data to be written in said image memory and allowing data write/read operations independently, and first and second read cache memory blocks for respectively storing image data read out from said image memory and allowing write/read operations independently;

memory control means;

write cache switching means for alternately switching and connecting said first and second write cache memory blocks to the processor and said memory control means to simultaneously execute write access and read access to said write cache memory block;

read cache switching means for alternately switching and connecting said first and second read cache memory blocks to the processor and said memory control means so as to allow the processor and said memory control means to simultaneously execute read access and write access to said read cache memory block; and

hit detection means for detecting a cache hit/cache miss depending on whether data, read access of which is requested by said CPU of the host computer or said drawing processor, is stored in said cache memory; and

said memory control means, being connected to said cache memory, said image memory, and said hit detection means for replacing contents of said cache memory by transferring image data stored in said image memory to said cache memory in response to a cache miss detected by said hit detection means.

8. A system according to claim 7, wherein said memory control means comprises prefetch means for reading out image data, succeeding image data stored in one of said first and second read cache memory blocks which is read-accessed by the processor, from said image memory, and prefetching the image data to the other of said first and second read cache memory blocks.

9. A system according to claim 8, wherein said prefetch means read-accesses said image memory in the page mode and continuously transfers a plurality of continuous image data from said image memory to the other of said first and second read cache memory blocks in the order of addresses.

10. A system according to claim 8, further comprising hit detection means for detecting a cache hit/cache miss depending on whether data, read access of which is requested by the processor, is stored in said cache memory block connected to the processor, and

wherein in response to said read cache miss detected by said hit detection means, said read cache switching means switches said read cache memory block connected to the processor to said read cache memory block, to which the image data is prefetched by said prefetch means.

11. A system according to claim 7, further comprising hit detection means for detecting a cache hit/cache miss depending on whether data write-requested by the processor is data on the same display line as that of data stored in said write cache memory block connected to the processor, and

wherein in response to a cache miss detected by said hit detection means, said write cache switching means switches said write cache memory block to which the processor is connected to the other write cache memory block.

12. A system according to claim 11, wherein said memory control means writes image data, stored in said write cache memory block newly connected to said memory control means, in said image memory in response to connection switching of a write cache memory block by said write cache switching means.

13. A display control system comprising:

an image memory for storing image data generated by a CPU of a host computer including said display control system and a drawing processor arranged in said display control system;

display means for displaying the image data, stored in said image memory, on a display;

a cache memory for storing part of the image data stored in said image memory, said cache memory being designed such that the image data is read/written therefrom/therein in accordance with a read/write request from said CPU of said host computer or said drawing processor, said cache memory being constituted by first to fourth cache memory blocks, each allowing the processor to read/write data therefrom/therein and having a maximum data width of n (n is a positive integer not less than eight) bits;

hit detection means for detecting a cache hit/cache miss depending on whether data, read access of which is requested by said CPU of the host computer or said drawing processor, is stored in said cache memory; and

memory control means, connected to said cache memory, said image memory, and said hit detection means for replacing contents of said cache memory by transferring image data stored in said image memory to said cache memory in response to a cache miss detected by said hit detection means, said memory control means reading out image data stored in said third and fourth cache memory blocks in units of 2 n bits and writes the image data in said image memory while the processor writes image data, which are to be written in said image memory, in said first and second cache memory blocks in units of 2 n bits.

14. A display control system comprising:

an image memory for storing image data generated by a processor;

display means for displaying the image data, stored in said image memory, on a display;

a cache memory for storing the image data read out from said image memory, said cache memory being designed such that the image data is read/written therefrom/therein in accordance with a read/write request from the processor;

access mode determination means, including a latch storing previous address data and a comparator for comparing the previous address data with new address supplied from the processor, for determining, in accordance with a history of changes in read address supplied from the processor, whether read access is performed by the processor in a continuous access mode in which continuous data are sequentially read out in an increasing or decreasing order of addresses; and

prefetch means for reading out image data succeeding image data read-requested by the processor from said image memory and prefetching the image data to said cache memory when said access mode determination means determines the continuous access mode.

15. A system according to claim 14, wherein said access mode determination means further includes a history circuit which stores the comparison results from the comparator, and determines whether read access is performed by the processor in a continuous access mode based on the comparison results stored in the history circuit.

16. A display control system connected through a local bus to a CPU of a host computer, comprising:

a multi-ported image memory for storing image data generated by the CPU and transferred to the image memory through said local bus;

a drawing processor arranged in said display control system for accelerating drawing functions;

display means for displaying the image data, stored in said image memory, on a display;

memory control means including a cache memory for storing part of the image data stored in said image memory, said cache memory being designed such that the image data is read/written therefrom/therein in accordance with a read/write request from said CPU of said host computer or said drawing processor, the cache memory storing data by comparing a write row address to a fixed tag and storing the data corresponding to the row address if the comparison produces a match, storing column addresses as tag data in tag entries for use in page mode access of the multi-ported image memory; and

hit detection means for detecting a cache hit/cache miss depending on whether data, read access of which is requested by said CPU of the host computer or said drawing processor, is stored in said cache memory; and

said memory control means being connected to said cache memory, said image memory, and said hit detection means for replacing contents of said cache memory, by transferring image data stored in said image memory to said cache memory in response to a cache miss detected by said hit detection means.