Data transmission system selecting both source and destination using addressing mechanism

• US 5,559,962 A
• Filed: 06/07/1995
• Issued: 09/24/1996
• Est. Priority Date: 10/09/1989
• Status: Expired due to Fees

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Funada, Takeshi, Kageyama, Yasuo, Okamura, Yashikoi, Suzuki, Takashi, Fujimori, Junichi
• Primary Examiner(s): Barry, Lance Leonard
• Application Number:
  US08/487,660
• Time in Patent Office: 475 Days
• Field of Search: 395/200.05, 395/200.07, 395/200.12, 395/200.15, 395/200.16, 395/290, 395/800, 395/200.01, 395/200.06, 395/200.08, 395/280, 395/287, 395/293 , 395/873, 395/431, 395/438, 395/484, 340/825.06, 340/825.07, 340/825.52
• US Class Current: 709/245
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A data transmission system includes a main controlling unit for producing pieces of address information, each piece of address information being indicative of a first address for a data source and a second address for a destination. The data transmission system further includes a plurality of component units assigned individual addresses, respectively, and a timing controlling unit sequentially supplying the pieces of address information to the component units at predetermined timings. In operation, one of the component units with the individual address matched with the first address serves as the data source and another component unit with the individual address matched with the second address serves as the destination communicating with the data source.

Claims

1. A data transmission system comprising:

a) main controlling means for providing pieces of address information, each piece of address information including a first address for a data source and a second address for a data destination, said main controlling means further providing mode information indicative of information included in said second address,

b) bus means having an address bus and a data bus,

c) a plurality of component units assigned individual addresses, and broadcasting data, respectively, and individually connected with said bus means for communicating with one another,

d) timing controlling means outputting a timing signal,

e) address controlling means receiving said pieces of address information supplied from said main controlling means, and responsive to said timing signal for sequentially supplying said pieces of address information through said bus means to said component units at predetermined timings, said address controlling means further comprising memory means for storing said pieces of address information, and for cyclically reading said pieces of address information out from said memory means to said address bus in response to said timing signal, said memory means including a plurality of random access memories, said main controlling means being operative to rewrite one of said random access memories while the pieces of address information are read out from another of said random access memories, to thereby selectively and simultaneously read out and rewrite said pieces of address information stored in said plurality of random access memories in response to said timing signal,

f) each of said plurality of component units further including a means for receiving each of said pieces of address information from said address controlling means and for checking each of said pieces of address information to determine whether the individual address assigned thereto matches said first address or said second address, and

g) each of said plurality of component units further including means for supplying data to said data bus when said first address matches said individual address assigned thereto and for receiving data from said data bus in response to said mode information when said second address matches said individual address assigned thereto.

2. A data transmission system as set forth in claim 1, wherein said address controlling means further comprises:

switching means for switching said one of said random access memories to be read out.

3. A data transmission system as set forth in claim 1, in which one of said component units is an analog-to-digital converting unit, and in which one of said pieces of address information includes first and second addresses identical with those of a subsequent piece of address information, wherein a time interval between said one of said pieces of address information and said subsequent piece of address information is equal to a sampling period of said analog-to-digital converting unit.

4. A data transmission system as set forth in claim 3, in which said data transmission system is a sound synthesizing and recording/reproducing system of an electronic musical instrument.

5. A data transmission system as set forth in claim 1, in which one of said pieces of address information includes first and second addresses identical with first and second addresses of another piece of address information.

6. A data transmission system as set forth in claim 1, in which said address controlling means further comprises:

watching means for watching operational states of said component units, such that if a component unit continues to operate, said watching means interrupts said sequential supplying of said pieces of address information.

7. A data transmission system as set forth in claim 6, in which each of said component units further includes:

a driver unit supplying a busy signal indicative of a continuation of operation of said component unit itself, and in which said watching means interrupts said sequential supplying when said busy signal is present at said predetermined timings.

8. A data transmission system comprising:

a) main controlling means for providing pieces of address information, each piece of address information including a first address for a data source and a second address for a data destination, said main controlling means further providing mode information indicative of information included in said second address,

b) bus means having an address bus and a data bus,

c) a plurality of component units assigned individual addresses, and broadcasting data, respectively, and individually connected with said bus means for communicating with one another,

d) timing controlling means outputting a timing signal,

e) address controlling means receiving said pieces of address information supplied from said main controlling means, and responsive to said timing signal for sequentially supplying said pieces of address information through said bus means to said component units at predetermined timings,

f) each of said plurality of component units further including a means for receiving each of said pieces of address information from said address controlling means and for checking each of said pieces of address information to determine whether the individual address assigned thereto matches said first address or said second address, and

g) each of said plurality of component units further including means for supplying data to said data bus when said first address matches said individual address assigned thereto and for receiving data from said data bus in response to said mode information when said second address matches said individual address assigned thereto, wherein one of said component units is an analog-to-digital converting unit, and one of said pieces of address information includes first and second addresses identical with those of a subsequent piece of address information, and wherein a time interval between said one of said pieces of address information and said subsequent piece of address information is equal to a sampling period of said analog-to-digital converting unit.

9. A data transmission system as set forth in claim 8, in which said data transmission system is a sound synthesizing and recording/reproducing system.

10. A data transmission system as set forth in claim 8, in which one of said pieces of address information includes first and second addresses identical with first and second addresses of another piece of address information.

11. A data transmission system as set forth in claim 8, in which said address controlling means further comprises:

watching means for watching operational states of said component units, such that if a component unit continues to operate, said watching means interrupts said sequential supplying of said pieces of address information.

12. A data transmission system as set forth in claim 8, in which each of said component units further includes:

a driver unit supplying a busy signal indicative of a continuation of operation of said component unit itself, and in which said watching means interrupts said sequential supplying when said busy signal is present at said predetermined timings.