Data processing system and method thereof

• US 5,559,973 A
• Filed: 04/17/1995
• Issued: 09/24/1996
• Est. Priority Date: 03/31/1993
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gallup, Micheal G., Seaton, Robert W. Jr., Tomazin, Thomas J., Goke, L. Rodney
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/425,004
• Time in Patent Office: 526 Days
• Field of Search: 395/375, 395/800
• US Class Current: 712/241
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 : Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A method for executing a repeat instruction in a data processor, comprising the steps of:

i) receiving the repeat instruction at a first address in a program, the repeat instruction having a first operand and a second operand;

ii) decoding the repeat instruction to provide a plurality of control signals;

iii) accessing a data value stored in a storage location indicated by the second operand of the repeat instruction in response to the plurality of control signals;

iv) executing the following steps for a preselected number of times, the preselected number of times being provided by the second operand of the repeat instruction.

v) sequentially executing a plurality of instructions, a first one of the plurality of instructions being at a second address and a last one of the plurality of instructions being at a third address, the second address being an address following the first address and the third address being based upon the first operand of the repeat instruction;

vi) asserting an enable value corresponding to a storage location accessed during execution of the last one of the plurality of instructions, the enable value selectively enabling the storage location to participate in execution of the one of the plurality of instructions; and

vii) negating a history value corresponding to the storage location accessed during execution of the last one of the plurality of instructions, the history value indicating whether the storage location has been used previously in execution of a instruction.

2. The method of claim 1 wherein the repeat instruction has the mnemonic form of "repeate".

3. The method of claim 1 wherein the data processor does not execute an operation specified by the last one of the plurality of instructions when the last one of the plurality of instructions is a vector instruction.

4. The method of claim 1 wherein the second operand is stored in a scalar register in the data processor.

5. The method of claim 1 wherein the first operand is an offset value which is added to a program counter value.

6. The method of claim 1 further comprising the step of:

executing a next instruction at a fourth address following the third address.

7. The method of claim 1 wherein the first operand is specified as a field in the repeat instruction.

8. The method of claim 1 wherein steps iv) through vii) are not executed when the second operand is equal to a value of zero.

9. The method of claim 1 wherein the last one of the plurality of instructions, step vi) and step vii) are all executed concurrently.

10. The method of claim 1 further comprising the step of:

asserting a status value during execution of the repeat instruction.