Apparatus and method for protecting data in a memory address range
First Claim
Patent Images
1. A data protection apparatus comprising:
- a processor addressing an address space, a memory area comprising a first memory, a bus interconnecting the processor and said first memory, a first address decoder generating a first selection signal in response to addresses in a first range of said first memory selected by the processor;
a second address decoder generating a second selection signal in response to addresses in a second range of addresses of said first memory selected by the processor, said second range of addresses being nonidentical to the first range of addresses and having at least one address in common with the first range; and
a protection circuit operatively coupled to the processor to receive a request signal therefrom, said protection circuit annunciating the event of generation of a second selection signal in the absence of receipt of a request signal.
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Abstract
A data protection apparatus has chip select logic, a protection circuit and one or more memory devices. The chip select logic is designed so that when protected memory is addressed, more than one selection signal is generated. In this way, a protected memory area may encompass all, or a portion, of one or more memory devices. The additional selection signal is processed by a protection circuit which will interrupt the processor if protected memory is addressed during a write cycle in the absence of a request signal which the processor is programmed to generate just prior to its writing to a protected memory area.
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Citations
64 Claims
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1. A data protection apparatus comprising:
- a processor addressing an address space, a memory area comprising a first memory, a bus interconnecting the processor and said first memory, a first address decoder generating a first selection signal in response to addresses in a first range of said first memory selected by the processor;
a second address decoder generating a second selection signal in response to addresses in a second range of addresses of said first memory selected by the processor, said second range of addresses being nonidentical to the first range of addresses and having at least one address in common with the first range; and
a protection circuit operatively coupled to the processor to receive a request signal therefrom, said protection circuit annunciating the event of generation of a second selection signal in the absence of receipt of a request signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
- a processor addressing an address space, a memory area comprising a first memory, a bus interconnecting the processor and said first memory, a first address decoder generating a first selection signal in response to addresses in a first range of said first memory selected by the processor;
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50. A method for use with a data protection apparatus comprising a processor addressing an address space, a first memory, a bus interconnecting the processor and said first memory, a first address decoder generating a first selection signal in response to addresses in a first range of said first memory selected by the processor, a second address decoder generating a second selection signal in response to addresses in a second range of addresses of said first memory selected by the processor, said second range of addresses being nonidentical to the first range of addresses and having at least one address in common with the first range, and a protection circuit operatively coupled to the processor to receive a request signal therefrom, the method comprising the steps of:
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addressing an address in the second range of addresses; generating the second selection signal in the second address decoder; and annunciating in the protection circuit whether the second selection signal has been generated in the absence of receipt of a request signal. - View Dependent Claims (51, 52, 53, 54, 55, 56, 57, 58)
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59. A method for protecting a memory region, said method for use with a data protection apparatus comprising a processor addressing an address space, at least one memory area comprising a first memory, a bus interconnecting the processor and said first memory, a first address decoder generating a first selection signal in response to addresses in a first range of said first memory selected by the processor, a second address decoder generating a second selection signal in response to addresses in a second range of addresses of said first memory selected by the processor, said second range of addresses being nonidentical to the first range of addresses and having at least one address in common with the first range, and a protection circuit operatively coupled to the processor to receive a request signal therefrom, the method comprising the steps of:
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generating a request signal; addressing an address in the second range of addresses during a write cycle; generating the second selection signal in the second address decoder; annunciating, by said protection circuit, the event of generation of the second selection signal in the absence of receipt of the request signal; and writing to an address in the second range of addresses only in the absence of the protection circuit annunciation. - View Dependent Claims (60, 61, 62, 63)
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64. A method for use with a data protection apparatus comprising a processor, a memory device, a protection circuit operatively coupled to the processor to receive a request signal therefrom, and an address decoder generating a selection signal corresponding to a protected region of the memory device, the protected region comprising less than all of the addresses of the memory device, the method comprising the steps of:
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addressing an address in the protected region of the memory device during a write cycle; providing an output signal annunciating whether the request signal has been received by the protection circuit prior to the addressing step; and interrupting the processor if no request signal has been received prior to the addressing step.
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Specification