System and method for designing a printed-circuit board

• US 5,559,997 A
• Filed: 10/04/1994
• Issued: 09/24/1996
• Est. Priority Date: 10/04/1993
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nishimura, Yuichi, Sueda, Nobuo, Saito, Yoshiyuki, Yoshimura, Hiroyuki, Tsuchida, Masayuki, Uemura, Hirokazu, Miura, Shinji
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US08/317,859
• Time in Patent Office: 721 Days
• Field of Search: 395/500, 395/61, 395/900, 395/921, 395/23, 395/51, 395/800, 395/919, 364/488, 364/489, 364/490, 364/578, 364/491, 361/777, 361/818
• US Class Current: 716/112
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H05K 1/023 using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 3/0005 for designing circuits by computer

Abstract

According to the printed-circuit board of the preset invention, the circuit modification unit 120 adds a noise reduction component, based on circuit board information inputted to the design information input unit 106. Then, the layout unit 132 sets a layout after the design rule generation unit 133 generates a design rule. The rated value modification unit 124 determines rated values of noise reduction components in accordance with the layout. Thus, design rule generation, noise reduction component addition, and rated value determination are automatically performed to satisfy the electric characteristics of evaluation targets. Consequently, interactive process in designing is reduced and the efficiency of designing can be realized.

Claims

1. A system for designing a circuit board, based on circuit board information, noise reduction information, and evaluation information, said circuit board information indicating a board to be used for a circuit board to be designed, a circuit to be laid out on the board, and components to be included in the circuit, said noise reduction information indicating anti-noise solution, said evaluation information indicating electric characteristics of the circuit board in process of designing, said system comprising:

an input means for receiving said circuit board information, said noise reduction information, and said evaluation information;

noise reduction component addition means for adding noise reduction components to the circuit described in said circuit board information, based on information on noise reduction components described in the received noise reduction information, and for modifying the circuit board information in accordance with the noise reduction components-added circuit;

a layout means for (1) laying out components and routes on the board described by said circuit board information, based on the circuit board information which has been modified by said noise reduction component addition means, and another information on restrictions to the layout described in said noise reduction information, for (2) generating layout information, using locations of the components and the routes laid out on the board as coordinate values, and for (3) further modifying the circuit board information modified by said noise reduction component addition means in accordance with the laid out circuit;

an evaluation means for evaluating electric characteristics of evaluation targets in the circuit described by said layout information and the circuit board information at that moment, based on said evaluation information on the electric characteristics of the circuit board in the process of designing;

rated value modification means for replacing the noise reduction components with other noise reduction components having different rated values, based on information on noise reduction components in said noise reduction information, and for modifying said circuit board information in accordance with the circuit having changed rated values;

a control means for starting said evaluation means every time said layout means completes a layout, and for starting said evaluation means every time said rated value modification means changes a rated value of a noise reduction component in the circuit;

an output means for outputting said circuit board information and said layout information when the electric characteristics of predetermined evaluation targets among the evaluation targets in the circuit described in said circuit board information and said layout information have been fairly evaluated by said evaluation means.

2. The system of claim 1, wherein said noise reduction component addition means comprises:

a noise reduction component-added-position recognition unit for recognizing a position which is supposed to be added a noise reduction component by comparing information indicating a position on the circuit to be added a noise reduction component, said information belonging to said noise reduction information with the inputted circuit board information;

a noise reduction component recognition unit for recognizing a noise reduction component which has been already added to a position recognized by said noise reduction component-added-position recognition unit;

a noise reduction component addition unit for adding a noise reduction component to the recognized position that has not been added a noise reduction component yet, based on information indicating a noise reduction component to be added and another information indicating a rated value of the noise reduction component to be added;

a priority assigning unit for assigning priorities to the noise reduction components recognized by said noise reduction component recognition unit and a noise reduction component newly added by said noise reduction component addition unit; and

a first circuit board information modification unit for adding said information indicating the priorities to said information describing the noise reduction components in the circuit board information, and for, when said noise reduction component addition unit has newly added a noise reduction component, modifying the inputted circuit board information in accordance with the circuit having the newly added noise reduction component; and

wherein said layout means comprises;

a layout area recognition unit for recognizing an area on the board which is described in the circuit board information and which can lay out components included in the circuit described in said circuit board information modified by said first circuit board information modification unit and routes to connect the components;

a layout unit for laying out the components included in the circuit described in said circuit board information and the routes to connect the components, in accordance with a restriction to the layout described in said noise reduction information, the components and the routes being laid out on the area recognized by said layout area recognition unit;

a layout judging unit for judging whether or not the layout of all necessary components and routes can be completed;

a noise reduction component deletion unit for sequentially deleting deletable noise reduction components in the circuit described in the circuit board information modified by said first circuit board information modification unit, starting at a noise reduction component which has been assigned a lowest priority, when the layout has been judged not to be able to be completed;

a layout information generation unit for generating layout information, using as coordinate values locations of the components and the routes laid out on the board by said layout unit;

a second circuit board information modification unit for further modifying the circuit board information modified by said first circuit board information modification unit by adding information indicating deleted noise reduction components to the information describing noise reduction components included in the circuit of said circuit board information;

a layout control unit for starting said layout area recognition unit, said layout unit, and said layout judging unit every time said noise reduction component deletion unit deletes a noise reduction component.

3. The system of claim 2, wherein said rated value modification means further comprises:

a rated value modification unit for replacing the noise reduction components added to the evaluation targets whose electric characteristics have been poorly evaluated by said evaluation means, with other noise reduction components having different rated values, based on information described in said noise reduction information;

(1) information indicating noise reduction components which can be replaced by other noise reduction components having different rated values, (2) information indicating a range of the different rated values; and

a third circuit board information modification unit for modifying said circuit board information modified by said second circuit board information modification unit in accordance with the circuit including a noise reduction component having a modified rated value.

4. The system of claim 3 further comprising:

a layout modification control unit for starting said layout means to lay out again the circuit described in said circuit board information at that point onto a location different from a location described in said layout information, when electric characteristics of a predetermined evaluation target have not been fairly evaluated by said evaluation means, even after all modifiable rated values of noise reduction components are modified;

a deleted noise reduction component re-addition unit for re-adding the deleted noise reduction components to evaluation targets whose electric characteristics have been poorly evaluated, the addition starting at a noise reduction component assigned a highest priority;

priority order change unit for changing an order of priorities assigned to the re-added noise reduction components into a different order indicating impossibility of deleting the noise reduction components;

a fourth circuit board information modification unit for (1) changing information added by said second circuit board information modification unit, said information indicating that a noise reduction component has been deleted, into information indicating the deleted noise reduction component has been re-added, and for (2) changing a priority order in the information describing noise reduction components into the priority order changed by said priority order change unit; and

deleted noise reduction component re-addition control unit for (1) putting said rated value modification unit stand-by after a completion of a layout by said layout means based on a direction of said layout modification control unit, and an evaluation performed by said evaluation means subsequent to the layout, for (2) starting said layout means every time said deleted noise reduction component re-addition control means re-adds a deleted noise reduction component to the circuit, and for (3) starting said rated value modification unit if said evaluation means does not fairly evaluate the electric characteristics of a predetermined evaluation target in the circuit to which all noise reduction components that can be re-added have been re-added.

5. The system of claim 4, wherein said noise reduction component addition means further comprises a first circuit evaluation unit for circuit-simulating a part including the recognized noise reduction component-to-be-added position in a circuit, said part being a circuit evaluation target described in said evaluation information, thereby determining whether an output of the circuit simulation for the circuit evaluation target satisfies a circuit evaluation rule described in said evaluation information, and for, when the circuit evaluation target does not satisfy the circuit evaluation rule, making said noise reduction component addition unit add a predetermined noise reduction component to the recognized noise reduction component-to-be-added position, based on the information indicating noise reduction components to be added, and the information indicating a rated value of the noise reduction component to be added.

6. The system of claim 5, wherein said noise reduction component addition means further comprises:

a second circuit evaluation unit for circuit-simulating the part in the circuit to which the noise reduction component has been added, in order to determine whether an output of the circuit simulation for a predetermined circuit evaluation target satisfies a predetermined circuit evaluation rule, thereby evaluating the electric characteristics of the part;

a noise reduction component rated value modification unit for replacing all noise reduction components having changeable rated values with other noise reduction components having different rated values when said second circuit evaluation unit poorly evaluated the electric characteristics of the part of the circuit; and

a noise reduction component rated value modification control unit for making said circuit evaluation unit evaluate the electric characteristics of the part including the noise reduction components having the different rated values, every time a noise reduction component is replaced with another noise reduction component having a different rated value.

7. The system of claim 6, wherein said rated value modification means further comprises:

a garbage noise reduction component recognition unit for detecting a rated value of a noise reduction component added to an evaluation target whose electric characteristics have been fairly evaluated, by replacing a noise reduction component having a changeable rated value with another noise reduction component having a different rated value, for comparing the detected rated value with information indicating a range of the rated value when the replaced noise reduction component becomes useless as a result of the replacement, said information being described in the inputted noise reduction information, and for recognizing, as garbage noise reduction component, the noise reduction component whose rated value has been put in the range of the rated value indicated in said information; and

a garbage noise reduction component deletion unit for deleting noise reduction components recognized by said garbage noise reduction component recognition unit and for modifying said circuit board information in accordance with the circuit from which the noise reduction components have been deleted as garbage noise reduction components, and for starting said layout means.

8. The system of claim 7 further comprising:

a design rule generation information input unit for receiving design rule generation information which indicates targets for which to generate design rules and also indicates a parameter for determining an allowable range of values for the targets such as a length of parallel routes, said design rules being restrictions in laying out a circuit on the board, described in inputted circuit board information;

design rule generation unit for simulating a design rule generation target predetermined in accordance with said design rule generation information every time a possible value of the design rule generation target is changed by every predetermined value under said parameter, continuing the changing operation of the values of the design rule generation target and the evaluation through simulation until a result of a simulation satisfies the predetermined design rule generation evaluation standard, and for generating a design rule, using a reference value when the result satisfies the predetermined design rule generation evaluation standard as an allowable value for the design rule generation target; and

design rule output unit for, when the result of the simulation does not satisfy the predetermined design rule generation evaluation standard even if the value of the design rule is changed to every possible value within the range, outputting a situation, and for outputting the generated design rule and for directing said layout means to set a layout based on the generated design rule, when the result of the simulation satisfies the predetermined design rule generation evaluation standard.

9. The system of claim 8, wherein said evaluation means comprises a transmission line simulator for obtaining by calculations an output waveform when a predetermined input waveform is given to a net which connects terminals of each component in the circuit, based on location of components in a circuit actually laid out in a board, length of routes, conditions of connections among layers, physical shapes of foils, and dielectric constant of the board, a simulation carried out by said evaluation means including a transmission line simulation carried out by said transmission line simulator.

10. The system of claim 9, wherein said design rule generation unit comprises a transmission line simulator for obtaining by calculations an output waveform when a predetermined input waveform is given to a net which connects terminals of each component in the circuit, based on location of components in a circuit actually laid out in a board, length of routes, conditions of connections among layers, physical shapes of foils, and dielectric constant of the board, a simulation carried out by said design rule generation unit including a transmission line simulation carried out by said transmission line simulator.

11. The system of claim 7 further comprising:

a design rule generation information input unit for receiving design rule generation information, which is used for generating a design rule indicating layout restrictions to be observed in laying out a circuit on the board described in inputted circuit board information, said design rule generation information indicating targets for which to generate design rules and parameter for determining a range of possible values of the targets, such as a length of parallel routes;

a design rule storage unit for storing a design rule corresponding to a predetermined value of said parameter for every predetermined design rule generation target;

a design rule generation unit for reading from said design rule storage unit a design rule to be determined by said parameter, based on the inputted design rule generation information, thereby making the read design rule into a design rule for said design rule generation target; and

a design rule output unit for outputting the generated design rule and for directing said layout means to set a layout based on the generated design rule.

12. The system of claim 8, wherein said evaluation means further comprises:

an evaluation rule storage unit for storing types of noise reduction components added in the circuit including said evaluation targets and a range of rated values of the added noise reduction components, for every predetermined evaluation target;

evaluation target recognition unit for recognizing an evaluation target in the circuit described by said layout information and said circuit board information at that point, based on information described in said evaluation information indicating an evaluation target in the laid out circuit; and

an evaluation unit for evaluating the electric characteristics of said evaluation targets by determining whether or not the types and rated values of the noise reduction components satisfy the evaluation rule stored in said evaluation storage unit.

13. The system of claim 4, wherein said noise reduction component addition means further comprises:

a second circuit evaluation unit for circuit-simulating the part in the circuit to which the noise reduction component has been added, in order to determine whether an output of the circuit simulation for a predetermined circuit evaluation target satisfies a predetermined circuit evaluation rule, thereby evaluating the electric characteristics of the part;

a noise reduction component rated value modification unit for replacing all noise reduction components having changeable rated values with other noise reduction components having different rated values when said second circuit evaluation unit poorly evaluated the electric characteristics of the part of the circuit; and

a noise reduction component rated value modification control unit for making said circuit evaluation unit evaluate the electric characteristics of the part including the noise reduction components having the different rated values, every time a noise reduction component is replaced with another noise reduction component having a different rated value.

14. The system of claim 4 further comprising:

a design rule generation information input unit for receiving design rule generation information which indicates targets for which to generate design rules and also indicates a parameter for determining an allowable range of values for the targets such as a length of parallel routes, said design rules being restrictions in laying out a circuit on the board, described in inputted circuit board information;

design rule generation unit for simulating a design rule generation target predetermined in accordance with said design rule generation information every time a possible value of the design rule generation target is changed by every predetermined value under said parameter, continuing the changing operation of the values of the design rule generation target and the evaluation through simulation until a result of a simulation satisfies the predetermined design rule generation evaluation standard, and for generating a design rule, using a reference value when the result satisfies the predetermined design rule generation evaluation standard as an allowable value for the design rule generation target; and

design rule output unit for, when the result of the simulation does not satisfy the predetermined design rule generation evaluation standard even if the value of the design rule is changed to every possible value within the range, outputting a situation, and for outputting the generated design rule and for directing said layout means to set a layout based on the generated design rule, when the result of the simulation satisfies the predetermined design rule generation evaluation standard.

15. The system of claim 14, wherein wherein said design rule generation unit comprises a transmission line simulator for obtaining by calculations an output waveform when a predetermined input waveform is given to a net which connects terminals of each component in the circuit, based on location of components in a circuit actually laid out in a board, length of routes, conditions of connections among layers, physical shapes of foils, and dielectric constant of the board, a simulation carried out by said design rule generation unit including a transmission line simulation carried out by said transmission line simulator.

16. The system of claim 4 further comprising:

a design rule generation information input unit for receiving design rule generation information, which is used for generating a design rule indicating layout restrictions to be observed in laying out a circuit on the board described in inputted circuit board information, said design rule generation information indicating targets for which to generate design rules and parameter for determining a range of possible values of the targets, such as a length of parallel routes;

a design rule storage unit for storing a design rule corresponding to a predetermined value of said parameter for every predetermined design rule generation target;

a design rule generation unit for reading from said design rule storage unit a design rule to be determined by said parameter, based on the inputted design rule generation information, thereby making the read design rule into a design rule for said design rule generation target; and

a design rule output unit for outputting the generated design rule and for directing said layout means to set a layout based on the generated design rule.

17. The system of claim 4, wherein said rated value modification means further comprises:

a garbage noise reduction component recognition unit for detecting a rated value of a noise reduction component added to an evaluation target whose electric characteristics have been fairly evaluated, by replacing a noise reduction component having a changeable rated value with another noise reduction component having a different rated value, for comparing the detected rated value with information indicating a range of the rated value when the replaced noise reduction component becomes useless as a result of the replacement, said information being described in the inputted noise reduction information, and for recognizing, as garbage noise reduction component, the noise reduction component whose rated value has been put in the range of the rated value indicated in said information; and

a garbage noise reduction component deletion unit for deleting noise reduction components recognized by said garbage noise reduction component recognition unit and for modifying said circuit board information in accordance with the circuit from which the noise reduction components have been deleted as garbage noise reduction components, and for starting said layout means.

18. The system of claim 2, wherein said noise reduction component addition means further comprises a first circuit evaluation unit for circuit-simulating a part including the recognized noise reduction component-to-be-added position in a circuit, said part being a circuit evaluation target described in said evaluation information, thereby determining whether an output of the circuit simulation for the circuit evaluation target satisfies a circuit evaluation rule described in said evaluation information, and for, when the circuit evaluation target does not satisfy the circuit evaluation rule, making said noise reduction component addition unit add a predetermined noise reduction component to the recognized noise reduction component-to-be-added position, based on the information indicating noise reduction components to be added, and the information indicating a rated value of the noise reduction component to be added.

19. The system of claim 2, wherein said noise reduction component addition means further comprises:

a second circuit evaluation unit for circuit-simulating the part in the circuit to which the noise reduction component has been added, in order to determine whether an output of the circuit simulation for a predetermined circuit evaluation target satisfies a predetermined circuit evaluation rule, thereby evaluating the electric characteristics of the part;

a noise reduction component rated value modification unit for replacing all noise reduction components having changeable rated values with other noise reduction components having different rated values when said second circuit evaluation unit poorly evaluated the electric characteristics of the part of the circuit; and

a noise reduction component rated value modification control unit for making said circuit evaluation unit evaluate the electric characteristics of the part including the noise reduction components having the different rated values, every time a noise reduction component is replaced with another noise reduction component having a different rated value.

20. The system of claim 2, wherein said rated value modification means further comprises:

a garbage noise reduction component recognition unit for detecting a rated value of a noise reduction component added to an evaluation target whose electric characteristics have been fairly evaluated, by replacing a noise reduction component having a changeable rated value with another noise reduction component having a different rated value, for comparing the detected rated value with information indicating a range of the rated value when the replaced noise reduction component becomes useless as a result of the replacement, said information being described in the inputted noise reduction information, and for recognizing, as garbage noise reduction component, the noise reduction component whose rated value has been put in the range of the rated value indicated in said information; and

a garbage noise reduction component deletion unit for deleting noise reduction components recognized by said garbage noise reduction component recognition unit and for modifying said circuit board information in accordance with the circuit from which the noise reduction components have been deleted as garbage noise reduction components, and for starting said layout means.

21. The system of claim 1 further comprising:

a design rule generation information input unit for receiving design rule generation information which indicates targets for which to generate design rules and also indicates a parameter for determining an allowable range of values for the targets such as a length of parallel routes, said design rules being restrictions in laying out a circuit on the board, described in inputted circuit board information;

design rule generation unit for simulating a design rule generation target predetermined in accordance with said design rule generation information every time a possible value of the design rule generation target is changed by every predetermined value under said parameter, continuing the changing operation of the values of the design rule generation target and the evaluation through simulation until a result of a simulation satisfies the predetermined design rule generation evaluation standard, and for generating a design rule, using a reference value when the result satisfies the predetermined design rule generation evaluation standard as an allowable value for the design rule generation target; and

design rule output unit for, when the result of the simulation does not satisfy the predetermined design rule generation evaluation standard even if the value of the design rule is changed to every possible value within the range, outputting a situation, and for outputting the generated design rule and for directing said layout means to set a layout based on the generated design rule, when the result of the simulation satisfies the predetermined design rule generation evaluation standard.

22. The system of claim 21, wherein said design rule generation unit comprises a transmission line simulator for obtaining by calculations an output waveform when a predetermined input waveform is given to a net which connects terminals of each component in the circuit, based on location of components in a circuit actually laid out in a board, length of routes, conditions of connections among layers, physical shapes of foils, and dielectric constant of the board, a simulation carried out by said design rule generation unit including a transmission line simulation carried out by said transmission line simulator.

23. The system of claim 1 further comprising:

a design rule generation information input unit for receiving design rule generation information, which is used for generating a design rule indicating layout restrictions to be observed in laying out a circuit on the board described in inputted circuit board information, said design rule generation information indicating targets for which to generate design rules and parameter for determining a range of possible values of the targets, such as a length of parallel routes;

a design rule storage unit for storing a design rule corresponding to a predetermined value of said parameter for every predetermined design rule generation target;

a design rule generation unit for reading from said design rule storage unit a design rule to be determined by said parameter, based on the inputted design rule generation information, thereby making the read design rule into a design rule for said design rule generation target; and

a design rule output unit for outputting the generated design rule and for directing said layout means to set a layout based on the generated design rule.

24. The system of claim 1, wherein said rated value modification means further comprises:

a garbage noise reduction component recognition unit for detecting a rated value of a noise reduction component added to an evaluation target whose electric characteristics have been fairly evaluated, by replacing a noise reduction component having a changeable rated value with another noise reduction component having a different rated value, for comparing the detected rated value with information indicating a range of the rated value when the replaced noise reduction component becomes useless as a result of the replacement, said information being described in the inputted noise reduction information, and for recognizing, as garbage noise reduction component, the noise reduction component whose rated value has been put in the range of the rated value indicated in said information; and

a garbage noise reduction component deletion unit for deleting noise reduction components recognized by said garbage noise reduction component recognition unit and for modifying said circuit board information in accordance with the circuit from which the noise reduction components have been deleted as garbage noise reduction components, and for starting said layout means.

25. A method for designing a circuit board, based on circuit board information, noise reduction information, and evaluation information, said circuit board information indicating a board to be used for a circuit board to be designed, a circuit to be laid out on the board, and components to be included in the circuit, said noise reduction information indicating anti-noise solution, said evaluation information indicating electric characteristics of the circuit board in process of designing, said method comprising:

a receiving step for receiving said circuit board information, said noise reduction information, and said evaluation information;

a noise reduction component adding step for adding noise reduction components to the circuit described in said circuit load information, based of information on noise reduction components described in the received noise reduction information, and modifying the circuit board information in accordance with the noise reduction components-added circuit;

a layout step for laying out components and routes on the board described by said circuit board information, based on the circuit board information which has been modified, and another information on restrictions to the layout described in said noise reduction information, generating layout information, using locations of the components and the routes laid out on the board as coordinate values, and further modifying the circuit board information modified in said noise reduction component adding step in accordance with the laid out circuit;

an evaluating step for evaluating electric characteristics of evaluation targets in the circuit described by said layout information and the circuit board information at that moment, based on said evaluation information on the electric characteristics of the circuit board in the process of designing;

a rated value modifying step for replacing the noise reduction components with other noise reduction components having different rated values, based on information on noise reduction components in said noise reduction information, and for modifying said circuit board information in accordance with the circuit having changed rated values; and

an output step for outputting said circuit board information and said layout information when the electric characteristics of predetermined evaluation targets among the evaluation targets in the circuit described in said circuit board information and said layout information have been fairly evaluated.

26. The method of claim 25, wherein said noise reduction component adding step comprises:

a noise reduction component added-position recognizing sub step for recognizing a position which is supposed to be added a noise reduction component by comparing information indicating a position on the circuit to be added a noise reduction component, said information belonging to said noise reduction information with the inputted circuit board information,

a noise reduction component recognizing sub step for recognizing a noise reduction component which has been already added to a position recognized in said noise reduction component-added-position recognizing sub step;

a noise reduction component adding sub step for adding a noise reduction component to the recognized position that has not been added a noise reduction component yet, based on information indicating a noise reduction component to be added and another information indicating a rated value of the noise reduction component to be added;

an assigning sub step for assigning priorities to the noise reduction components recognized in said noise reduction component recognizing sub step and a noise reduction component newly added in said noise reduction component adding sub step; and

a first circuit board information modifying sub step for first adding said information indicating the priorities to said information describing the noise reduction components in the circuit board information, and when said noise reduction component adding sub step has newly added a noise reduction component, modifying the inputted circuit board information in accordance with the circuit having the newly added noise reduction component; and

wherein said layout step comprises;

a layout area recognizing sub step for recognizing an area on the board which is described in the circuit board information and which can lay out components included in the circuit described in said circuit board information modified in said first circuit board information modifying sub step and routes to connect the components;

a layout sub step for laying out the components included in the circuit described in said circuit board information and the routes to connect the components, in accordance with a restriction to the layout described in said noise reduction information, the components and the routes being laid out on the area recognized in said layout area recognizing sub step;

a layout judging sub step for judging whether or not the layout of all necessary components and routes can be completed;

a noise reduction component deletion sub step for sequentially deleting deletable noise reduction components in the circuit described in the circuit board information modified in said first circuit board information modifying sub step, starting at a noise reduction component which has been assigned a lowest priority, when the layout has been judged not to be able to be completed;

for executing operations of said layout sub step every time a noise reduction component is deleted, continuing the deleting operation until a layout has been judged to be able to be completed in said layout judging sub step, and for, when the completion of a layout has been judged to be impossible even after all the deletable noise reduction components are deleted, outputting the situation;

a layout information generating sub step for generating layout information, using as coordinate values locations of the components and the routes laid out on the board in said layout sub step; and

a second circuit board information modifying sub step for further modifying the circuit board information modified in said first circuit board information modifying sub step by adding information indicating deleted noise reduction components to the information describing noise reduction components included in the circuit of said circuit board information, every time a noise reduction component is deleted in said noise reduction component deletion sub step.

27. The method of claim 26, wherein said rated value modifying step further comprises:

a rated value modifying sub step for repeating an evaluating operation in said evaluating step every time a noise reduction component added to the evaluation target whose electric characteristics have been poorly evaluated in said evaluating step is replaced with other noise reduction components having different rated values, based on information described in said noise reduction information;

(1) information indicating noise reduction components which can be replaced by other noise reduction components having different rated values, (2) information indicating a range of the different rated values, and continuing the replacement until the electric characteristics of the evaluation target is fairly evaluated in said evaluating step; and

a third circuit board information modifying sub step for modifying said circuit board information modified in said second circuit board information modifying step in accordance with the circuit including a noise reduction component having a modified rated value;

a layout modifying sub step for starting said layout step to lay out again the circuit described in said circuit board information at that point onto a location different from a location described in said layout information, when electric characteristics of a predetermined evaluation target have not been fairly evaluated in said evaluating step, even after all modifiable rated values of noise reduction components are modified;

a deleted noise reduction component re-adding step for making said evaluating step evaluate all evaluation targets included in the circuit which has been laid out again in said layout step, for re-adding the deleted noise reduction components to evaluation targets whose electric characteristics have been poorly evaluated, starting at a noise reduction component assigned a highest priority, executing said layout step to lay out re-added noise reduction components every time a noise reduction component is re-added and evaluating the laid out circuit, thus continuing the re-adding operation until the electric characteristics of the predetermined evaluation targets are fairly evaluated;

priority order changing unit for changing an order of priorities assigned to the re-added noise reduction components into a different order indicating impossibility of deleting the noise reduction components, every time a noise reduction component is re-added;

a fourth circuit board information modifying step for (1) changing information added in said second circuit board information modifying substep, said information indicating that a noise reduction component has been deleted, into information indicating the deleted noise reduction component has been re-added, said information being in said circuit board information modified in said second circuit board information modifying sub step, every time a noise reduction component is re-added; and

wherein

when the electric characteristics of all the evaluation targets in the circuit to which the once deleted noise reduction components have been re-added are not fairly evaluated, sub steps from said rate value modifying sub step to said fourth circuit board information modifying step are repeated until the electric characteristics of the predetermined valuation targets are fairly evaluated.

28. The method of claim 27, wherein said noise reduction component adding step further comprises a first circuit evaluating sub step for circuit-simulating a part including the recognized noise reduction component-to-be-added position in a circuit, thereby determining whether an output of the circuit simulation for the circuit evaluation target satisfies a predetermined circuit evaluation rule, and for, when the circuit evaluation target does not satisfy the circuit evaluation rule, adding a predetermined noise reduction component to the noise reduction component-to-be-added position recognized in said noise reduction component recognizing sub step, based on the information indicating noise reduction components to be added, and the information indicating a rated value of the noise reduction component to be added.

29. The method of claim 28, wherein said noise reduction component adding step further comprises:

a second circuit evaluation sub step for circuit-simulating the part in the circuit to which the noise reduction component has been added, in order to determine whether an output of the circuit simulation for a predetermined circuit evaluation target satisfies a predetermined circuit evaluation rule, thereby evaluating the electric characteristics of the part;

a noise reduction component rated value modifying sub step for replacing all noise reduction components having changeable rated values with other noise reduction components having different rated values when the electric characteristics of the part of the circuit have been poorly evaluated in said second circuit evaluating step, for circuit simulating a part including a noise reduction component replaced by another noise reduction component having a different rated value, for continuing the changing operation of rated values and the evaluating operation in said second circuit evaluating sub step until the electric characteristics of all the evaluation targets are fairly evaluated in said circuit evaluating sub step.

30. The method of claim 29, wherein said rated value modifying step further comprises:

a garbage noise reduction component recognizing sub step for detecting a rated value of a noise reduction component added to an evaluation target whose electric characteristics have been fairly evaluated, by replacing a noise reduction component having a changeable rated value with another noise reduction component having a different rated value, for comparing the detected rated value with information indicating a range of the rated value when the replaced noise reduction component becomes useless as a result of the replacement, said information being described in the inputted noise reduction information, and for recognizing, as garbage noise reduction component, the noise reduction component whose rated value has been put in the range of the rated value indicated in said information; and

a garbage noise reduction component deleting sub step for deleting noise reduction components recognized by said garbage noise reduction component recognizing sub step, and for modifying said circuit board information in accordance with the circuit from which the noise reduction components have been deleted as garbage noise reduction components.

31. The method of claim 30 further comprising:

a design rule generation information input sub step for receiving design rule generation information which indicates targets for which to generate design rules and also indicates a parameter for determining an allowable range of values for the targets such as a length of parallel routes, said design rules being restrictions in laying out a circuit on the board, described in inputted circuit board information;

a design rule generating sub step for simulating a design rule generation target predetermined in accordance with said design rule generation information every time a possible value of the design rule generation target is changed by every predetermined value under said parameter, continuing the changing operation of the values of the design rule generation target and the evaluation through simulation until a result of a simulation satisfies the predetermined design rule generation evaluation standard, and for generating a design rule, using a reference value when the result satisfies the predetermined design rule generation evaluation standard as an allowable value for the design rule generation target; and

a design rule output sub step for, when the result of the simulation does not satisfy the predetermined design rule generation evaluation standard even if the value of the design rule is changed to every possible value within the range, outputting the situation, and for outputting the generated design rule and for directing said layout step to set a layout based on the generated design rule, when the result of the simulation satisfies the predetermined design rule generation evaluation standard.

32. The method of claim 31, wherein said evaluating step comprises a transmission line simulator for obtaining by calculations an output waveform when a predetermined input waveform is given to a net which connects terminals of each component in the circuit, based on location of components in a circuit actually laid out in a board, length of routes, conditions of connections among layers, physical shapes of foils, and dielectric constant of the board, a simulation carried out by said evaluating step being a transmission line simulation carried out by said transmission line simulator.

33. The method of claim 32, wherein said design rule generating sub step comprises a transmission line simulator for obtaining by calculations an output waveform when a predetermined input waveform is given to a net which connects terminals of each component in the circuit, based on location of components in a circuit actually laid out in a board, length of routes, conditions of connections among layers, physical shapes of foils, and dielectric constant of the board, a simulation carried out by said design rule generating step being a transmission line simulation carried out by said transmission line simulator.

34. The method of claim 30 further comprising:

a design rule generation information input sub step for receiving design rule generation information, which is used for generating a design rule indicating layout restrictions to be observed in laying out a circuit on the board described in inputted circuit board information, said design rule generation information indicating targets for which to generate design rules and parameter for determining a range of possible values of the targets, such as a length of parallel routes;

a design rule generating sub step for storing a design rule corresponding to a predetermined value of said parameter for every predetermined design rule generation target to memory, and for reading from said memory, based on the inputted design rule generation information, thereby making the read design rule into a design rule for said design rule generation target; and

a design rule output sub step for outputting the generated design rule and for directing said layout step to set a layout based on the generated design rule.

35. The method of claim 31, wherein said evaluation step further comprises:

evaluation target recognizing step for storing types of noise reduction components added in the circuit including said evaluation targets and a range of rated values of the added noise reduction components to memory for every predetermined evaluation target and for recognizing an evaluation target in the circuit described by said layout information and said circuit board information at that point, based on information described in said evaluation information indicating an evaluation target in the laid out circuit; and

an evaluating sub step for evaluating the electric characteristics of said evaluation targets by determining whether or not the types and rated values of the noise reduction components satisfy the evaluation rule stored in the memory.

36. The method of claim 27, wherein said noise reduction component adding step further comprises:

a second circuit evaluation sub step for circuit-simulating the part in the circuit to which the noise reduction component has been added, in order to determine whether an output of the circuit simulation for a predetermined circuit evaluation target satisfies a predetermined circuit evaluation rule, thereby evaluating the electric characteristics of the part;

a noise reduction component rated value modifying sub step for replacing all noise reduction components having changeable rated values with other noise reduction components having different rated values when the electric characteristics of the part of the circuit have been poorly evaluated in said second circuit evaluating step, for circuit simulating a part including a noise reduction component replaced by another noise reduction component having a different rated value, for continuing the changing operation of rated values and the evaluating operation in said second circuit evaluating sub step until the electric characteristics of all the evaluation targets are fairly evaluated in said circuit evaluating sub step.

37. The method of claim 27 further comprising:

a design rule generation information input sub step for receiving design rule generation information which indicates targets for which to generate design rules and also indicates a parameter for determining an allowable range of values for the targets such as a length of parallel routes, said design rules being restrictions in laying out a circuit on the board, described in inputted circuit board information;

a design rule generating sub step for simulating a design rule generation target predetermined in accordance with said design rule generation information every time a possible value of the design rule generation target is changed by every predetermined value under said parameter, continuing the changing operation of the values of the design rule generation target and the evaluation through simulation until a result of a simulation satisfies the predetermined design rule generation evaluation standard, and for generating a design rule, using a reference value when the result satisfies the predetermined design rule generation evaluation standard as an allowable value for the design rule generation target; and

a design rule output sub step for, when the result of the simulation does not satisfy the predetermined design rule generation evaluation standard even if the value of the design rule is changed to every possible value within the range, outputting the situation, and for outputting the generated design rule and for directing said layout step to set a layout based on the generated design rule, when the result of the simulation satisfies the predetermined design rule generation evaluation standard.

38. The method of claim 37, wherein said design rule generating sub step comprises a transmission line simulator for obtaining by calculations an output waveform when a predetermined input waveform is given to a net which connects terminals of each component in the circuit, based on location of components in a circuit actually laid out in a board, length of routes, conditions of connections among layers, physical shapes of foils, and dielectric constant of the board, a simulation carried out by said design rule generating step being a transmission line simulation carried out by said transmission line simulator.

39. The method of claim 27 further comprising:

a design rule generation information input sub step for receiving design rule generation information, which is used for generating a design rule indicating layout restrictions to be observed in laying out a circuit on the board described in inputted circuit board information, said design rule generation information indicating targets for which to generate design rules and parameter for determining a range of possible values of the targets, such as a length of parallel routes;

a design rule generating sub step for storing a design rule corresponding to a predetermined value of said parameter for every predetermined design rule generation target to memory, and for reading from said memory, based on the inputted design rule generation information, thereby making the read design rule into a design rule for said design rule generation target; and

a design rule output sub step for outputting the generated design rule and for directing said layout step to set a layout based on the generated design rule.

40. The method of claim 27, wherein said rated value modifying step further comprises:

a garbage noise reduction component recognizing sub step for detecting a rated value of a noise reduction component added to an evaluation target whose electric characteristics have been fairly evaluated, by replacing a noise reduction component having a changeable rated value with another noise reduction component having a different rated value, for comparing the detected rated value with information indicating a range of the rated value when the replaced noise reduction component becomes useless as a result of the replacement, said information being described in the inputted noise reduction information, and for recognizing, as garbage noise reduction component, the noise reduction component whose rated value has been put in the range of the rated value indicated in said information; and

a garbage noise reduction component deleting sub step for deleting noise reduction components recognized by said garbage noise reduction component recognizing sub step, and for modifying said circuit board information in accordance with the circuit from which the noise reduction components have been deleted as garbage noise reduction components.

41. The method of claim 26, wherein said noise reduction component adding step further comprises a first circuit evaluating sub step for circuit-simulating a part including the recognized noise reduction component-to-be-added position in a circuit, thereby determining whether an output of the circuit simulation for the circuit evaluation target satisfies a predetermined circuit evaluation rule, and for, when the circuit evaluation target does not satisfy the circuit evaluation rule, adding a predetermined noise reduction component to the noise reduction component-to-be-added position recognized in said noise reduction component recognizing sub step, based on the information indicating noise reduction components to be added, and the information indicating a rated value of the noise reduction component to be added.

42. The method of claim 26, wherein said noise reduction component adding step further comprises:

a second circuit evaluation sub step for circuit-simulating the part in the circuit to which the noise reduction component has been added, in order to determine whether an output of the circuit simulation for a predetermined circuit evaluation target satisfies a predetermined circuit evaluation rule, thereby evaluating the electric characteristics of the part;

a noise reduction component rated value modifying sub step for replacing all noise reduction components having changeable rated values with other noise reduction components having different rated values when the electric characteristics of the part of the circuit have been poorly evaluated in said second circuit evaluating step, for circuit simulating a part including a noise reduction component replaced by another noise reduction component having a different rated value, for continuing the changing operation of rated values and the evaluating operation in said second circuit evaluating sub step until the electric characteristics of all the evaluation targets are fairly evaluated in said circuit evaluating sub step.

43. The method of claim 26 further comprising:

a design rule generation information input sub step for receiving design rule generation information, which is used for generating a design rule indicating layout restrictions to be observed in laying out a circuit on the board described in inputted circuit board information, said design rule generation information indicating targets for which to generate design rules and parameter for determining a range of possible values of the targets, such as a length of parallel routes;

a design rule generating sub step for storing a design rule corresponding to a predetermined value of said parameter for every predetermined design rule generation target to memory, and for reading from said memory, based on the inputted design rule generation information, thereby making the read design rule into a design rule for said design rule generation target; and

a design rule output sub step for outputting the generated design rule and for directing said layout step to set a layout based on the generated design rule.

44. The method of claim 25 further comprising:

a design rule generation information input sub step for receiving design rule generation information which indicates targets for which to generate design rules and also indicates a parameter for determining an allowable range of values for the targets such as a length of parallel routes, said design rules being restrictions in laying out a circuit on the board, described in inputted circuit board information;

a design rule generating sub step for simulating a design rule generation target predetermined in accordance with said design rule generation information every time a possible value of the design rule generation target is changed by every predetermined value under said parameter, continuing the changing operation of the values of the design rule generation target and the evaluation through simulation until a result of a simulation satisfies the predetermined design rule generation evaluation standard, and for generating a design rule, using a reference value when the result satisfies the predetermined design rule generation evaluation standard as an allowable value for the design rule generation target; and

a design rule output sub step for, when the result of the simulation does not satisfy the predetermined design rule generation evaluation standard even if the value of the design rule is changed to every possible value within the range, outputting the situation, and for outputting the generated design rule and for directing said layout step to set a layout based on the generated design rule, when the result of the simulation satisfies the predetermined design rule generation evaluation standard.

45. The method of claim 44, wherein said design rule generating sub step comprises a transmission line simulator for obtaining by calculations an output waveform when a predetermined input waveform is given to a net which connects terminals of each component in the circuit, based on location of components in a circuit actually laid out in a board, length of routes, conditions of connections among layers, physical shapes of foils, and dielectric constant of the board, a simulation carried out by said design rule generating step being a transmission line simulation carried out by said transmission line simulator.

46. The method of claim 25 further comprising:

a design rule generation information input sub step for receiving design rule generation information, which is used for generating a design rule indicating layout restrictions to be observed in laying out a circuit on the board described in inputted circuit board information, said design rule generation information indicating targets for which to generate design rules and parameter for determining a range of possible values of the targets, such as a length of parallel routes;

a design rule generating sub step for storing a design rule corresponding to a predetermined value of said parameter for every predetermined design rule generation target to memory, and for reading from said memory, based on the inputted design rule generation information, thereby making the read design rule into a design rule for said design rule generation target; and

a design rule output sub step for outputting the generated design rule and for directing said layout step to set a layout based on the generated design rule.

47. The method of claim 25, wherein said rated value modifying step further comprises:

a garbage noise reduction component recognizing sub step for detecting a rated value of a noise reduction component added to an evaluation target whose electric characteristics have been fairly evaluated, by replacing a noise reduction component having a changeable rated value with another noise reduction component having a different rated value, for comparing the detected rated value with information indicating a range of the rated value when the replaced noise reduction component becomes useless as a result of the replacement, said information being described in the inputted noise reduction information, and for recognizing, as garbage noise reduction component, the noise reduction component whose rated value has been put in the range of the rated value indicated in said information; and

a garbage noise reduction component deleting sub step for deleting noise reduction components recognized by said garbage noise reduction component recognizing sub step, and for modifying said circuit board information in accordance with the circuit from which the noise reduction components have been deleted as garbage noise reduction components.